TAS5720MRSMT from Texas Instruments, in a VQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VREF_N	power_in	Negative reference for analog; connect to the VCOM and VREG capacitor negative pins.
2	FAULTZ	output	Open-drain active-low fault flag; pull up on the PCB with a resistor to DVDD.
3	SDZ	input	Active-low shutdown signal; assert low to hold the device inactive.
4	LRCLK	input	TDM interface frame synchronization.
5	MCLK	input	Device master clock.
6	BCLK	input	TDM interface serial bit clock.
7	SDIN	input	TDM interface data input.
8	SCL	input	I2C clock input; pull up on the PCB with a 2.4-kΩ resistor.
9	SDA	bidirectional	I2C bidirectional data; pull up on the PCB with a 2.4-kΩ resistor.
10	GND	power_in	Ground; connect to the PCB ground plane.
11	DVDD	power_in	Digital power supply; connect to a 3.3-V supply with an external decoupling capacitor.
12	ADR1	input	I2C address input that detects a short to DVDD, a short to GND, a 22-kΩ connection to GND, or a 22-kΩ connection to DVDD.
13	ADR0	input	I2C address input that detects a short to DVDD, a short to GND, a 22-kΩ connection to GND, or a 22-kΩ connection to DVDD.
14	PVDD	power_in	Class-D amplifier power supply input; connect to the PVDD supply and decouple externally.
15	PVDD	power_in	Class-D amplifier power supply input; connect to the PVDD supply and decouple externally.
16	OUT_N	output	Class-D amplifier negative output.
17	OUT_N	output	Class-D amplifier negative output.
18	BST_N	passive	Class-D amplifier negative bootstrap; connect a capacitor between BST_N and OUT_N.
19	PGND	power_in	Power ground; connect to the PCB ground plane.
20	PGND	power_in	Power ground; connect to the PCB ground plane.
21	PGND	power_in	Power ground; connect to the PCB ground plane.
22	PGND	power_in	Power ground; connect to the PCB ground plane.
23	BST_P	passive	Class-D amplifier positive bootstrap; connect a capacitor between BST_P and OUT_P.
24	OUT_P	output	Class-D amplifier positive output.
25	OUT_P	output	Class-D amplifier positive output.
26	PVDD	power_in	Class-D amplifier power supply input; connect to the PVDD supply and decouple externally.
27	PVDD	power_in	Class-D amplifier power supply input; connect to the PVDD supply and decouple externally.
28	AVDD	power_in	Analog power supply input; connect directly to PVDD.
29	GND	power_in	Ground; connect to the PCB ground plane.
30	GVDD	power_out	Class-D amplifier gate drive regulator output; connect a decoupling capacitor to the PCB ground plane.
31	VREG	power_out	Analog regulator output; connect a decoupling capacitor to the VREF_N pin.
32	VCOM	output	Common mode reference output; connect a decoupling capacitor to the VREF_N pin.
33	Thermal Pad	power_in	Exposed thermal pad; connect to GND for best system performance, and if not connected to GND, leave floating.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32-EP(4x4)
Category	Operational Amplifier/Comparator
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage PVDD, AVDD (TAS5720M)	PVDD, AVDD	-0.3		30	V	TAS5720M	6
Supply voltage DVDD	DVDD	-0.3		4	V		6
Digital input voltage		-0.5		0.5	V	Digital inputs referenced to DVDD supply; max printed as VDVDD + 0.5	6
Ambient operating temperature	TA	-25		85	°C		6
Storage temperature	Tstg	-40		125	°C		6
ESD HBM	V(ESD)	-4000		4000	V	Human body model, ANSI/ESDA/JEDEC JS-001	6
ESD CDM	V(ESD)	-1500		1500	V	Charged device model, JESD22-C101	6
Power supply voltage PVDD/AVDD (TAS5720M)	PVDD/AVDD	4.5		26.4	V	TAS5720M	6
Power supply voltage DVDD	DVDD	3	3.3	3.6	V		6
Minimum speaker load	RSPK	3.2			Ω		6
Operating free-air temperature	TA	-25		85	°C		6
Operating junction temperature	TJ	-25		150	°C		6
Junction-to-ambient thermal resistance	RθJA		37.3		°C/W	RSM (VQFN) 32 pins	6
Junction-to-case (top) thermal resistance	RθJCtop		30.4		°C/W		6
Junction-to-board thermal resistance	RθJB		7.9		°C/W		6
Junction-to-top characterization parameter	ψJT		0.4		°C/W		6
Junction-to-board characterization parameter	ψJB		7.7		°C/W		6
Junction-to-case (bottom) thermal resistance	RθJCbot		2.5		°C/W		6
Input logic high leakage	IIH			15	µA	All digital pins, excluding SDZ	7
Input logic low leakage	IIL	-15			µA	All digital pins, excluding SDZ	7
Input logic high leakage SDZ	IIH(SDZ)			1	µA	SDZ	7
Input logic low leakage SDZ	IIL(SDZ)	-1			µA	SDZ	7
High-level digital input threshold	VIH	70			% VDVDD	All digital pins	7
Low-level digital input threshold	VIL			30	% VDVDD	All digital pins	7
Output logic low FAULTZ	VOL			10	% VDVDD	Output IOL = -2 mA	7
Input capacitance digital inputs	CIN		5		pF	All digital pins	7
MCLK duty cycle	D(MCLK)	45	50	55	%		7
MCLK input frequency	f(MCLK)			25	MHz		7
BCLK duty cycle	D(BCLK)	45	50	55	%		7
BCLK input frequency	f(BCLK)			25	MHz		7
I2C load capacitance	CL(I2C)			400	pF	Allowable load capacitance for each I2C line	7
SCL frequency	fSCL			400	kHz	No wait states	7
Overtemperature error threshold	OTE(THRESH)		150		°C		7
Overtemperature error hysteresis	OTE(HYST)		15		°C		7
Overcurrent error threshold	OCE(THRESH)		6		A	V(PVDD) = 16.5 V, TA = 25°C	7
DC error threshold	DCE(THRESH)		2.6		V	V(PVDD) = 16.5 V, TA = 25°C	7
Channel-to-channel phase shift	φCC			0.2	deg	Output phase shift between multiple devices from 20 Hz to 20 kHz	8
Frequency response ripple	A(RIPPLE)	-0.15		0.15	dB	Maximum deviation above or below passband gain	8
Amplifier analog gain error	AV(ERROR)	-0.15		0.15	dB		9
DC output offset voltage	VOS			1.5	mV	Measured between OUTP and OUTN	9
Power stage FET on-resistance	RDS(on)FET		120		mΩ	TA = 25°C	9
Power stage total on-resistance	RDS(on)TOT		150		mΩ	TA = 25°C	9
Peak output current	IPK		5		A	TA = 25°C	9
Shutdown to Active Time	tACTIVE			25	ms	From deassertion of SDZ until the Class-D amplifier begins switching	10
Time high and low, BCLK, LRCLK, SDIN	tH_L	10			ns		10
Rise-time BCLK, LRCLK, SDIN inputs	tRISE			8	ns		10
Fall-time BCLK, LRCLK, SDIN inputs	tFALL			8	ns		10
I2C bus free time	tBUS	1.3			µs	Between start and stop conditions	10
I2C hold time SCL to SDA	tHOLD1(I2C)	80			ns		10
I2C hold time start condition to SCL	tHOLD2(I2C)	0.6			µs		10
I2C startup time after DVDD POR	tSTART(I2C)	12			ms		10
I2C rise time SCL and SDA	tRISE(I2C)			300	ns		10
I2C fall time SCL and SDA	tFALL(I2C)			300	ns		10
I2C setup SDA to SCL	tSU1(I2C)	100			ns		10
I2C setup SCL to start condition	tSU2(I2C)	0.6			µs		10
I2C setup SCL to stop condition	tSU3(I2C)	0.6			µs		10
SCL high pulse duration	tW(H)	0.6			µs		10
SCL low pulse duration	tW(L)	1.3			µs		10
Amplifier fault time-out period, DC detect error	tFAULTZ		650		ms	DC detect error	10
Amplifier fault time-out period, OTE or OCE fault	tFAULTZ		1.3		s	OTE or OCE fault	10

CAD (KiCad official)

Symbol: TAS5720MRSMT
Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
3D model: VQFN-32-EP(4x4) (KiCad packages3D, STEP)
3D model files: tas5720mrsmt-etched.step / tas5720mrsmt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tas5720mrsmt.step / tas5720mrsmt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (51 pp, sha256 a0b636659324c21c, retrieved 2026-10-31, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TAS5720MRSMT

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3D Model

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