component

ADP7102ARDZ-R7

Public Made by Adom

by adom

Analog Devices Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)adp7102ardz-r7factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

ADP7102ARDZ-R7

Analog Devices · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8-EP

ADP7102ARDZ-R7 from Analog Devices, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT power_out Regulated output voltage; bypass VOUT to GND with a 1 μF or greater capacitor.
2 SENSE/ADJ input SENSE measures the actual output voltage at the load and feeds the error amplifier (fixed-voltage versions only), while ADJ is set by an external resistor divider to program the output voltage (adjustable versions only).
3 GND power_in Ground.
4 NC unconnected No connect; do not connect to this pin.
5 EN/UVLO input Enable input: drive high to turn the regulator on and low to turn it off (connect to VIN for automatic startup); when used, the programmable UVLO upper and lower thresholds are set by the external programming resistors.
6 GND power_in Ground.
7 PG output Open-drain power-good output that requires an external pull-up resistor to VIN or VOUT and transitions low immediately in shutdown, current limit, thermal shutdown, or when the output falls below 90% of nominal; may be left open or grounded if unused.
8 VIN power_in Regulator input supply, operating from 3.3 V to 20 V; bypass VIN to GND with a 1 μF or greater capacitor.
9 EPAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-8-EP
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN 3.3 20 V 3
Operating supply current IGND 400 μA IOUT = 100 μA, VIN = 10 V 3
Operating supply current IGND 900 μA IOUT = 100 μA, VIN = 10 V, TJ = −40°C to +125°C 3
Operating supply current IGND 450 μA IOUT = 10 mA, VIN = 10 V 3
Operating supply current IGND 1050 μA IOUT = 10 mA, VIN = 10 V, TJ = −40°C to +125°C 3
Operating supply current IGND 650 μA IOUT = 150 mA, VIN = 10 V 3
Operating supply current IGND 1250 μA IOUT = 150 mA, VIN = 10 V, TJ = −40°C to +125°C 3
Operating supply current IGND 750 μA IOUT = 300 mA, VIN = 10 V 3
Operating supply current IGND 1400 μA IOUT = 300 mA, VIN = 10 V, TJ = −40°C to +125°C 3
Shutdown current IGND-SD 40 μA EN = GND, VIN = 12 V 3
Shutdown current IGND-SD 75 μA EN = GND, VIN = 12 V, TJ = −40°C to +125°C 3
Input reverse current IREV-INPUT 0.3 μA EN = GND, VIN = 0 V, VOUT = 20 V 3
Input reverse current IREV-INPUT 5 μA EN = GND, VIN = 0 V, VOUT = 20 V, TJ = −40°C to +125°C 3
Fixed output voltage accuracy VOUT -0.8 0.8 % IOUT = 10 mA 3
Fixed output voltage accuracy VOUT -2 1 % 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C 3
Adjustable output voltage accuracy VADJ 1.21 1.22 1.23 V IOUT = 10 mA 3
Adjustable output voltage accuracy VADJ 1.196 1.232 V 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C 3
Line regulation ΔVOUT/ΔVIN -0.015 0.015 %/V VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C 3
Load regulation ΔVOUT/ΔIOUT 0.2 %/A IOUT = 1 mA to 300 mA 3
Load regulation ΔVOUT/ΔIOUT 1 %/A IOUT = 1 mA to 300 mA, TJ = −40°C to +125°C 3
ADJ input bias current ADJI-BIAS 10 nA 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, ADJ connected to VOUT 3
SENSE input bias current SENSEI-BIAS 1 μA 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, SENSE connected to VOUT, VOUT = 1.5 V 3
Dropout voltage VDROPOUT 20 mV IOUT = 10 mA 3
Dropout voltage VDROPOUT 40 mV IOUT = 10 mA, TJ = −40°C to +125°C 3
Dropout voltage VDROPOUT 100 mV IOUT = 150 mA 3
Dropout voltage VDROPOUT 175 mV IOUT = 150 mA, TJ = −40°C to +125°C 3
Dropout voltage VDROPOUT 200 mV IOUT = 300 mA 3
Dropout voltage VDROPOUT 325 mV IOUT = 300 mA, TJ = −40°C to +125°C 3
Start-up time tSTART-UP 800 μs VOUT = 5 V 3
Current-limit threshold ILIMIT 450 575 750 mA 3
PG output logic high PGHIGH 1 V IOH < 1 μA 3
PG output logic low PGLOW 0.4 V IOL < 2 mA 3
PG output threshold, voltage falling PGFALL -9.2 % 3
PG output threshold, voltage rising PGRISE -6.5 % 3
Thermal shutdown threshold TSSD 150 °C TJ rising 4
Thermal shutdown hysteresis TSSD-HYS 15 °C 4
UVLO threshold rising UVLORISE 1.18 1.22 1.28 V 3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C 4
UVLO threshold falling UVLOFALL 1.13 V 3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C, 10 kΩ in series with enable pin 4
UVLO hysteresis current UVLOHYS 7.5 9.8 12 μA VEN > 1.25 V, TJ = −40°C to +125°C 4
Enable pulldown current IEN-IN 500 nA EN = VIN 4
Start threshold VSTART 3.2 V TJ = −40°C to +125°C 4
Shutdown threshold VSHUTDOWN 2.45 V TJ = −40°C to +125°C 4
Input voltage hysteresis 250 mV 4
Minimum input and output capacitance CMIN 0.7 μF TA = −40°C to +125°C 4
Capacitor ESR RESR 0.001 0.2 Ω TA = −40°C to +125°C 4
VIN to GND -0.3 22 V 5
VOUT to GND -0.3 20 V 5
EN/UVLO to GND -0.3 V 5
PG to GND -0.3 V 5
SENSE/ADJ to GND -0.3 V 5
Storage temperature range -65 150 °C 5
Operating junction temperature range -40 125 °C 5
Power supply rejection ratio PSRR 60 dB 10 kHz, VIN = 4.3 V, VOUT = 3.3 V 4
Power supply rejection ratio PSRR 50 dB 100 kHz, VIN = 4.3 V, VOUT = 3.3 V 4
Output noise voltage OUTNOISE 15 μV rms 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.8 V 4
Output noise voltage OUTNOISE 18 μV rms 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.5 V, adjustable mode 4
Output noise voltage OUTNOISE 65 μV rms 10 Hz to 100 kHz, VIN = 18 V, VOUT = 15 V, adjustable mode 4
Junction-to-ambient thermal resistance, 8-lead SOIC θJA 48.5 °C/W 5
Junction-to-case thermal resistance, 8-lead SOIC θJC 58.4 °C/W 5
Junction-to-board thermal characterization parameter, 8-lead SOIC ΨJB 31.3 °C/W 5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper of copper used to solder the package GND pins to the PCB. 21

CAD (KiCad official)

  • Symbol: ADP7102ARDZ-R7
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: adp7102ardz-r7-etched.step / adp7102ardz-r7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adp7102ardz-r7.step / adp7102ardz-r7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 5d2323fca1d98c66, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF