component
FP7126LR-G1
Public Made by Adomby adom
Advanced Analog Technology LED Drivers, SOT23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownFP7126LR-G1
Advanced Analog Technology · LED Drivers · SOT23-6
FP7126LR-G1 from Advanced Analog Technology, in a SOT23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIM | input | This pin is the linear and PWM dimming input of the IC; the datasheet gives DIM input low of 0.75 V max and high of 2.5 min at VDD=12 V, with an absolute maximum range of -0.3 V to 5.5 V. |
| 2 | GND | power_in | Ground return for all internal circuitry. |
| 3 | VDD | power_in | Power supply pin for all internal circuits, recommended to operate from 8 V to 12 V DC, with an absolute maximum of 16 V to GND and to be bypassed by a low ESR capacitor (10 uF). |
| 4 | CS | input | Current sense pin that senses the FET current through an external sense resistor, with the sense reference voltage of 250 mV typical and an absolute maximum range of -0.3 V to 5.5 V. |
| 5 | GND | power_in | Ground return for all internal circuitry; it must be connected to pin 2. |
| 6 | GATE | output | Output gate driver for an external N-channel power MOSFET, with an absolute maximum range of -0.3 V to VDD-0.3 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Advanced Analog Technology |
| Package | SOT23-6 |
| Category | LED Drivers |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supply Voltage | VDD | -0.3 | 16 | V | VDD to GND | 4 | |
| GATE pin voltage | -0.3 | V | 4 | ||||
| CS, DIM pin voltage | -0.3 | 5.5 | V | 4 | |||
| Allowable Power Dissipation | PD | 455 | mW | SOT23-6L TA≦+25°C | 4 | ||
| Junction Temperature | TJ | 150 | °C | 4 | |||
| Junction to Ambient Thermal Resistance | θJA | 220 | °C / W | 4 | |||
| Junction to Case Thermal Resistance | θJC | 150 | °C / W | 4 | |||
| Storage Temperature | TS | -40 | 150 | °C | SOT23-6L | 4 | |
| SOT23-6L Lead Temperature | 260 | °C | soldering, 10 sec | 4 | |||
| Supply Voltage | VDD | 8 | 12 | V | 5 | ||
| Ambient Operating Temperature | -25 | 85 | °C | 5 | |||
| Junction Operating Temperature | -25 | 125 | °C | 5 | |||
| VDD clamp voltage | VDD(clamp) | 11 | 12.8 | 14 | V | IIN(clamp)=2mA | 5 |
| Pin DIM input low voltage | VEN(lo) | 0.75 | V | VDD = 12V | 5 | ||
| Pin DIM input high voltage | VEN(hi) | 2.5 | V | VDD = 12V | 5 | ||
| Current sense reference voltage | VCS | 245 | 250 | 255 | mV | 5 | |
| GATE output rise time | tRISE | 30 | 50 | ns | CGATE = 500pF, VDD = 12V | 5 | |
| GATE output fall time | tFALL | 30 | 50 | ns | CGATE = 500pF, VDD = 12V | 5 | |
| VDD under voltage lockout threshold | UVLO | 11.1 | V | VDD rising | 5 | ||
| VDD under voltage lockout hysteresis | △ UVLO | 3.7 | V | 5 | |||
| Operation current | IIN(operation) | 0.5 | mA | VDD=11V、VCS=0V、DIM=5V、500pF to GATE | 5 | ||
| Minimum on-time | TON(min) | 0.5 | us | CS=VCS + 30mV | 5 | ||
| Minimum off-time | TOFF(min) | 0.5 | us | CS=0V | 5 | ||
| Hiccup threshold voltage | VCS | 600 | mV | 5 | |||
| Short circuit hiccup time | THICCUP | 1.2 | ms | 5 | |||
| Minimum on-time (short circuit) | TON(min) | 200 | ns | CS=5V | 5 | ||
| GATE sourcing current | ISOURCE | 165 | mA | VGATE = 0V, VDD = 12V | 5 | ||
| GATE sinking current | ISINK | 165 | mA | VGATE = VDD, VDD = 12V | 5 | ||
| Thermal shutdown | OTP | 160 | °C | VDD=12V | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 4. The GND of the RCS、 C1 and IC’s GND pin should be connected close and together directly to a ground plane. GND should pour copper as large area as possible. | 10 |
CAD (KiCad official)
- Symbol:
FP7126LR-G1 - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT23-6 (KiCad packages3D, STEP)
- 3D model files:
fp7126lr-g1-etched.step/fp7126lr-g1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);fp7126lr-g1.step/fp7126lr-g1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Advanced Analog Technology datasheet (12 pp, sha256
8ad394a43180a8b8, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).