component
LDTB113ZLT1G
Public Made by Adomby adom
LRC Digital Transistors, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLDTB113ZLT1G
LRC · Digital Transistors · SOT-23
LDTB113ZLT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BASE | input | Base is the input of the built-in bias resistor network (R1 = 1 kΩ), with input voltage rated from −10 V to +5 V. |
| 2 | EMITTER | passive | Emitter is the transistor emitter terminal, with the device rated for a supply voltage VCC of −50 V maximum and 200 mW power dissipation. |
| 3 | COLLECTOR | passive | Collector is the output terminal, with output current rated at −500 mA maximum (absolute maximum ratings, Ta = 25 °C). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
CAD (KiCad official)
- Symbol:
LDTB113ZLT1G - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
ldtb113zlt1g-etched.step/ldtb113zlt1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ldtb113zlt1g.step/ldtb113zlt1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LRC datasheet (3 pp, sha256
92239889a839d3c8, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).