component
ISL6506BCBZ-T
Public Made by Adomby adom
RENESAS Monitors & Reset Circuits, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownISL6506BCBZ-T
RENESAS · Monitors & Reset Circuits · SOIC-8-EP
ISL6506BCBZ-T from RENESAS, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | 5V bias supply from the ATX 5VSB output, well decoupled, which powers the IC and the internal 3V3AUX LDO and is monitored for power-on reset (falling POR 3.60 to 3.95V, rising max 4.5V). |
| 2 | 3V3AUX | bidirectional | Connects to the 3.3VDUAL output; regulated to 3.3V by the internal pass device in sleep states, fed from ATX 3.3V through an external NMOS in active states, and monitored for undervoltage (2.475V) in S3 and S4/S5. |
| 3 | S3 | input | Digital sleep-state control input with internal 10µA pull-down, connected to the system SLP_S3 signal (low threshold 0.8V, high threshold 2.2V, 0 to 5.5V range). |
| 4 | S5 | input | Digital sleep-state control input with internal 10µA pull-down, connected to the system SLP_S5 signal (low threshold 0.8V, high threshold 2.2V, 0 to 5.5V range). |
| 5 | GND | power_in | Signal ground for the IC and ground return for the internal 3V3AUX LDO; all voltages are measured with respect to it. |
| 6 | DLA | output | Open-drain output that needs a 1kΩ resistor to the ATX 12V rail to pull up the gates of the N-MOSFETs switching ATX 3.3V and 5V in active state, and that also monitors the 12V rail for POR (rising threshold 8.9 to 10.8V); absolute maximum is GND-0.3V to 14.5V. |
| 7 | 5VDLSB | output | Drives the gate of an external P-MOSFET that connects ATX 5VSB to the 5VDUAL output in S3 sleep state (also in S4/S5 for ISL6506A), with 20 to 35mA drive current. |
| 8 | N/C | unconnected | No internal connection. |
| 9 | GND | power_in | Exposed pad (EPAD) is ground and should be tied to the ground plane with three to five vias for thermal management. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | SOIC-8-EP |
| Category | Power Management ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Falling 5VSB POR Threshold | 3.6 | 3.95 | V | 3 | |||
| Rising 12V POR Threshold | 8.9 | 9.8 | 10.8 | V | 1.00kΩ resistor between DLA and 12V Rail | 3 | |
| Regulation | 2 | % | V5VSBY = 5.0V, I3V3SB = 0A | 3 | |||
| 3V3SB Overcurrent Trip | I3V3SB_TRIP | 2 | A | ISL6506B (Note 3) | 3 | ||
| 5VDLSB Output Drive Current | I5VDLSB | 20 | 35 | mA | V5VDLSB = 4V, V5VSB = 5V | 3 | |
| Soft-start Interval | tSS | 6.55 | 8.2 | 9.85 | ms | 3 | |
| High Level Input Threshold | 2.2 | V | 3 | ||||
| Low Level Input Threshold | 0.8 | V | 3 | ||||
| Rising 5VSB POR Threshold | 4.5 | V | 3 | ||||
| Supply Voltage tolerance | V5VSB | -5 | 5 | % | Printed as +5V ±5% | 3 | |
| Lowest 5VSB Supply Voltage Guaranteeing Parameters | 4.5 | V | 3 | ||||
| Digital Inputs | VSx | 0 | 5.5 | V | 3 | ||
| Ambient Temperature Range | 0 | 70 | °C | 3 | |||
| Junction Temperature Range | 0 | 125 | °C | 3 | |||
| Supply Voltage | V5VSB | 5 | V | Printed as +5V ±5% | 3 | ||
| Supply Voltage (Absolute Maximum) | V5VSB | 7 | V | 3 | |||
| DLA Voltage | DLA | -0.3 | 14.5 | V | min printed as GND - 0.3V | 3 | |
| All Other Pins Voltage | 7 | V | 3 | ||||
| Maximum Junction Temperature (Plastic Package) | 150 | °C | 3 | ||||
| Maximum Storage Temperature Range | -65 | 150 | °C | 3 | |||
| Thermal Resistance Junction-to-Ambient | θJA | 40 | °C/W | EPSOIC package (Notes 1, 2) | 3 | ||
| Thermal Resistance Junction-to-Case | θJC | 3.5 | °C/W | EPSOIC package (Notes 1, 2) | 3 |
CAD (KiCad official)
- Symbol:
ISL6506BCBZ-T - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
isl6506bcbz-t-etched.step/isl6506bcbz-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);isl6506bcbz-t.step/isl6506bcbz-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (8 pp, sha256
1c48d885586e7d63, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).