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Contents

README

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Si3585CDV-T1-GE3-VB

VBsemi Elec · MOSFETs · TSOP-6

Si3585CDV-T1-GE3-VB from VBsemi Elec, in a TSOP-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G1 input Gate of the N-channel MOSFET (Q1); VGS rated ±20 V maximum.
2 S2 passive Source of the P-channel MOSFET (Q2); VDS rated -20 V and continuous drain current -3.4 A at TA = 25 °C.
3 G2 input Gate of the P-channel MOSFET (Q2); VGS rated ±20 V maximum.
4 D2 passive Drain of the P-channel MOSFET (Q2); VDS rated -20 V and pulsed drain current 10 A.
5 S1 passive Source of the N-channel MOSFET (Q1); VDS rated 20 V and continuous drain current 5.5 A at TA = 25 °C.
6 D1 passive Drain of the N-channel MOSFET (Q1); VDS rated 20 V and pulsed drain current 15 A.

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package TSOP-6
Category Transistors/Thyristors
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage N-Ch VDS 20 V TA = 25 °C, N-Channel 1
Drain-Source Voltage P-Ch VDS -20 V TA = 25 °C, P-Channel 1
Gate-Source Voltage N-Ch VGS -20 20 V N-Channel 1
Gate-Source Voltage P-Ch VGS -20 20 V P-Channel 1
Continuous Source Current N-Ch IS 1.05 A Diode conduction, N-Channel 1
Continuous Source Current P-Ch IS -1.05 A Diode conduction, P-Channel 1
Maximum Power Dissipation PD 1.15 W TA = 25 °C 1
Maximum Power Dissipation PD 0.73 W TA = 70 °C 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Junction-to-Ambient Thermal Resistance RthJA 93 110 °C/W t ≤ 5 s 1
Junction-to-Ambient Thermal Resistance RthJA 130 150 °C/W Steady State 1
Junction-to-Lead Thermal Resistance RthJL 75 90 °C/W Steady State 1
Gate Threshold Voltage N-Ch VGS(th) 0.5 0.8 1.5 V VDS = VGS, ID = 250 µA 2
Gate Threshold Voltage P-Ch VGS(th) -1.5 -0.8 -0.5 V VDS = VGS, ID = - 250 µA 2
Gate-Body Leakage N-Ch IGSS -100 100 nA VDS = 0 V, VGS = ± 8 V 2
Gate-Body Leakage P-Ch IGSS -100 100 nA VDS = 0 V, VGS = ± 8 V 2
Zero Gate Voltage Drain Current N-Ch IDSS 1 µA VDS = 16 V, VGS = 0 2
Zero Gate Voltage Drain Current P-Ch IDSS -1 µA VDS = - 16 V, VGS = 0 2
Zero Gate Voltage Drain Current N-Ch IDSS 5 µA VDS = 16 V, VGS = 0 V, TJ = 55 °C 2
Zero Gate Voltage Drain Current P-Ch IDSS -5 µA VDS = - 16 V, VGS = 0 V, TJ = 55 °C 2
Diode Forward Voltage N-Ch VSD 0.81 1.1 V IS = 1.05 A, VGS = 0 V 2
Diode Forward Voltage P-Ch VSD -1.1 -0.83 V IS = - 1.05 A, VGS = 0 V 2
Total Gate Charge N-Ch Qg 2.1 3.2 nC VDS = 15 V, VGS = 5 V, ID = 1.8 A 2
Total Gate Charge P-Ch Qg 2.4 3.6 nC VDS = - 15 V, VGS = - 5 V, ID = - 1.8 A 2
Turn-On Delay Time N-Ch td(on) 7 11 ns VDD = 15 V, RL = 15 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω 2
Turn-On Delay Time P-Ch td(on) 8 12 ns VDD = - 15 V, RL = 15 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω 2
Rise Time N-Ch tr 9 14 ns VDD = 15 V, RL = 15 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω 2
Rise Time P-Ch tr 12 18 ns VDD = - 15 V, RL = 15 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω 2
Turn-Off Delay Time N-Ch td(off) 13 20 ns VDD = 15 V, RL = 15 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω 2
Turn-Off Delay Time P-Ch td(off) 12 18 ns VDD = - 15 V, RL = 15 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω 2
Fall Time N-Ch tf 5 8 ns VDD = 15 V, RL = 15 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω 2
Fall Time P-Ch tf 7 11 ns VDD = - 15 V, RL = 15 Ω, ID ≅ - 1 A, VGEN = - 10 V, Rg = 6 Ω 2
Source-Drain Reverse Recovery Time N-Ch trr 35 60 ns IF = 1.05 A, dI/dt = 100 A/µs 2
Source-Drain Reverse Recovery Time P-Ch trr 30 60 ns IF = - 1.05 A, dI/dt = 100 A/µs 2
Gate-Source Charge N-Ch Qgs 0.7 nC VDS = 15 V, VGS = 5 V, ID = 1.8 A 2
Gate-Drain Charge N-Ch Qgd 0.7 nC VDS = 15 V, VGS = 5 V, ID = 1.8 A 2

CAD (KiCad official)

  • Symbol: Si3585CDV-T1-GE3-VB
  • Footprint: Package_SO:TSOP-6_1.65x3.05mm_P0.95mm
  • 3D model: TSOP-6 (KiCad packages3D, STEP)
  • 3D model files: si3585cdv-t1-ge3-vb-etched.step / si3585cdv-t1-ge3-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si3585cdv-t1-ge3-vb.step / si3585cdv-t1-ge3-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (10 pp, sha256 556b78e312129a11, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF