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TPS7A8300ARGWR
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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, VQFN-20(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPS7A8300ARGWR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · VQFN-20(5x5)
TPS7A8300ARGWR from Texas Instruments, in a VQFN-20(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Regulated output pin; a 47-µF or larger ceramic capacitor (25 µF of capacitance or greater) from OUT to ground is required for stability. |
| 2 | SNS | input | Output voltage sense input that connects to the internal R1 resistor; connect it to the load side of the output trace only if ANY-OUT is used, otherwise leave it floating. |
| 3 | FB | input | Feedback pin connected to the error amplifier; a 10-nF feed-forward capacitor from FB to OUT is optional but maximizes ac performance. |
| 4 | PG | output | Active-high open-drain power-good output that indicates when the output voltage reaches VIT(PG) of the target. |
| 5 | 50mV | input | ANY-OUT voltage setting pin for the 50 mV bit of the internal feedback network; connect to GND or SNS, or leave floating when not in use. |
| 6 | 100mV | input | ANY-OUT voltage setting pin for the 100 mV bit of the internal feedback network; connect to GND or SNS, or leave floating when not in use. |
| 7 | 200mV | input | ANY-OUT voltage setting pin for the 200 mV bit of the internal feedback network; connect to GND or SNS, or leave floating when not in use. |
| 8 | GND | power_in | Ground pin that must be connected to ground, the thermal pad, and each other with a low-impedance connection. |
| 9 | 400mV | input | ANY-OUT voltage setting pin for the 400 mV bit of the internal feedback network; connect to GND or SNS, or leave floating when not in use. |
| 10 | 800mV | input | ANY-OUT voltage setting pin for the 800 mV bit of the internal feedback network; connect to GND or SNS, or leave floating when not in use. |
| 11 | 1.6V | input | ANY-OUT voltage setting pin for the 1.6 V bit of the internal feedback network; connect to GND or SNS, or leave floating when not in use. |
| 12 | BIAS | power_in | BIAS supply voltage that enables low-input low-output operation and improves ac and dc performance for VIN ≤ 2.2 V; a 1-µF capacitor (0.47-µF minimum) to ground is required, and the pin must be left floating or tied to ground if unused. |
| 13 | NR/SS | passive | Noise-reduction and soft-start pin; an external capacitor to ground reduces reference noise and enables soft start, with 10 nF or larger recommended. |
| 14 | EN | input | Enable pin; driving it to logic high enables the device and driving it to logic low disables it, and it must be connected to IN or BIAS if enable control is not required. |
| 15 | IN | power_in | Input supply voltage pin; a 10-µF or larger ceramic capacitor (5 µF of capacitance or greater) from IN to ground is required. |
| 16 | IN | power_in | Input supply voltage pin; a 10-µF or larger ceramic capacitor (5 µF of capacitance or greater) from IN to ground is required. |
| 17 | IN | power_in | Input supply voltage pin; a 10-µF or larger ceramic capacitor (5 µF of capacitance or greater) from IN to ground is required. |
| 18 | GND | power_in | Ground pin that must be connected to ground, the thermal pad, and each other with a low-impedance connection. |
| 19 | OUT | output | Regulated output pin; a 47-µF or larger ceramic capacitor (25 µF of capacitance or greater) from OUT to ground is required for stability. |
| 20 | OUT | output | Regulated output pin; a 47-µF or larger ceramic capacitor (25 µF of capacitance or greater) from OUT to ground is required for stability. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20(5x5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply voltage range | VIN | 1.1 | 6.5 | V | 6 | ||
| Bias supply voltage range | VBIAS | 3 | 6.5 | V | 6 | ||
| Output voltage range (TPS7A8400A) [printed name] | VOUT | 0.8 | 5.2 | V | Does not include device accuracy or feedback resistor accuracy | 6 | |
| Enable voltage range | VEN | 0 | V | Upper limit is VIN | 6 | ||
| Output current | IOUT | 0 | 2 | A | 6 | ||
| Input capacitor | CIN | 10 | 22 | µF | 6 | ||
| Output capacitor | COUT | 22 | µF | 6 | |||
| Bias pin capacitor | CBIAS | 1 | 10 | µF | 6 | ||
| Power-good pullup resistance | RPG | 10 | 100 | kΩ | 6 | ||
| Bottom resistor value in feedback network (upper limit) | R2 | 160 | kΩ | Upper limit for adjustable operation | 6 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 6 | ||
| Input voltage, IN, BIAS, PG, EN | -0.3 | 7 | V | 6 | |||
| Input voltage, IN, BIAS, PG, EN (5% duty cycle, pulse duration 200 µs) | -0.3 | 7.5 | V | 5% duty cycle, pulse duration = 200 µs | 6 | ||
| Voltage, NR/SS, FB | -0.3 | 3.6 | V | 6 | |||
| Voltage, SNS, OUT | -0.3 | V | Upper limit VIN + 0.3 V (or 7.0 V, whichever is smaller) | 6 | |||
| Voltage, 50mV, 100mV, 200mV, 400mV, 800mV, 1.6V pins | -0.3 | V | Upper limit VOUT + 0.3 V | 6 | |||
| PG sink current into device | 5 | mA | Sink current into device | 6 | |||
| Operating junction temperature range (absolute maximum) | TJ | -55 | 150 | °C | 6 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 6 | ||
| Accuracy | -1 | 1 | % | 0.8 V ≤ VOUT ≤ 5.2 V, 5 mA ≤ IOUT ≤ 2 A, over VIN | 8 | ||
| Accuracy with BIAS | -0.75 | 0.75 | % | 1.1 V ≤ VIN ≤ 2.2 V, 5 mA ≤ IOUT ≤ 2 A, 3.0 V ≤ VBIAS ≤ 6.5 V | 8 | ||
| Output current limit | ILIM | 2.8 | 3.3 | 3.8 | A | VOUT forced at 0.9 × VOUT(nom), VIN = VOUT(nom) + 0.4 V | 8 |
| Dropout voltage | VDO | 200 | mV | VIN = 1.4 V, IOUT = 2 A, VFB = 0.8 V, 3% | 8 | ||
| Dropout voltage | VDO | 300 | mV | VIN = 5.5 V, IOUT = 2 A, VFB = 0.8 V, 3% | 8 | ||
| Dropout voltage | VDO | 125 | mV | VIN = 1.1 V, VBIAS = 5 V, IOUT = 2 A, VFB = 0.8 V, 3% | 8 | ||
| EN pin current | IEN | -0.1 | 0.1 | µA | VIN = 6.5 V, VEN = 0 V and 6.5 V | 7 | |
| EN pin low-level input voltage (disable device) | VIL(EN) | 0 | 0.5 | V | Disable device | 7 | |
| EN pin high-level input voltage (enable device) | VIH(EN) | 1.1 | 6.5 | V | Enable device | 7 | |
| PG pin low-level output voltage | VOL(PG) | 0.4 | V | VOUT < VIT(PG), IPG = -1 mA (current into device) | 7 | ||
| PG pin leakage current | Ilkg(PG) | 1 | µA | VOUT > VIT(PG), VPG = 6.5 V | 7 | ||
| NR/SS pin charging current | INR/SS | 4 | 6.6 | 9 | µA | VNR/SS = GND, VIN = 6.5 V | 7 |
| FB pin leakage current | IFB | -100 | 100 | nA | VIN = 6.5 V | 7 | |
| GND pin current | IGND | 2.8 | 4 | mA | VIN = 6.5 V, IOUT = 5 mA | 8 | |
| GND pin current in shutdown | IGND | 1.2 | 25 | µA | Shutdown, PG = open, VIN = 6.5 V, VEN = 0.5 V | 8 | |
| Junction-to-ambient thermal resistance | RθJA | 33.4 | °C/W | RGW (VQFN) 20 pins | 7 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 24.9 | °C/W | RGW (VQFN) 20 pins | 7 | ||
| Junction-to-board thermal resistance | RθJB | 13 | °C/W | RGW (VQFN) 20 pins | 7 | ||
| Junction-to-top characterization parameter | ψJT | 0.4 | °C/W | RGW (VQFN) 20 pins | 7 | ||
| Junction-to-board characterization parameter | ψJB | 13 | °C/W | RGW (VQFN) 20 pins | 7 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 3.9 | °C/W | RGW (VQFN) 20 pins | 7 | ||
| Top resistor value in feedback network | R1 | 12.1 | kΩ | Adjustable operation; 12.1-kΩ resistor selected to optimize PSRR and noise | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side, copper surface. The use of vias and long traces to the input and output capacitors is stro | 48 |
CAD (KiCad official)
- Symbol:
TPS7A8300ARGWR - Footprint:
Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm - 3D model: VQFN-20(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps7a8300argwr-etched.step/tps7a8300argwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a8300argwr.step/tps7a8300argwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (63 pp, sha256
4b23b1f5239092dc, retrieved 2026-11-05, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).