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CY8C27443-24PVXIT

Public Made by Adom

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Cypress Semicon CYPRESS, SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscy8c27443-24pvxitfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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CY8C27443-24PVXIT

Cypress Semicon · CYPRESS · SSOP-28-208mil

CY8C27443-24PVXIT from Cypress Semicon, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0[7] bidirectional Analog column mux input on GPIO port 0 bit 7.
2 P0[5] bidirectional Analog column mux input and column output on GPIO port 0 bit 5.
3 P0[3] bidirectional Analog column mux input and column output on GPIO port 0 bit 3.
4 P0[1] bidirectional Analog column mux input on GPIO port 0 bit 1.
5 P2[7] bidirectional General-purpose digital I/O pin P2[7]; the datasheet lists no additional analog or special function for this pin.
6 P2[5] bidirectional General-purpose digital I/O pin P2[5]; the datasheet lists no additional analog or special function for this pin.
7 P2[3] bidirectional Direct switched capacitor block input on GPIO port 2 bit 3.
8 P2[1] bidirectional Direct switched capacitor block input on GPIO port 2 bit 1.
9 SMP power_out Switch mode pump connection that requires external components.
10 P1[7] bidirectional I2C SCL on GPIO port 1 bit 7.
11 P1[5] bidirectional I2C SDA on GPIO port 1 bit 5.
12 P1[3] bidirectional General-purpose digital I/O pin P1[3]; the datasheet lists no additional function for this pin.
13 P1[1] bidirectional Crystal input (XTALin), I2C SCL and ISSP-SCLK; the ISSP pins are not High Z at POR.
14 VSS power_in Ground connection.
15 P1[0] bidirectional Crystal output (XTALout), I2C SDA and ISSP-SDATA; the ISSP pins are not High Z at POR.
16 P1[2] bidirectional General-purpose digital I/O pin P1[2]; the datasheet lists no additional function for this pin.
17 P1[4] bidirectional Optional external clock input (EXTCLK).
18 P1[6] bidirectional General-purpose digital I/O pin P1[6]; the datasheet lists no additional function for this pin.
19 XRES input Active high external reset with internal pull down.
20 P2[0] bidirectional Direct switched capacitor block input on GPIO port 2 bit 0.
21 P2[2] bidirectional Direct switched capacitor block input on GPIO port 2 bit 2.
22 P2[4] bidirectional External analog ground (AGND) connection.
23 P2[6] bidirectional External voltage reference (VREF) connection.
24 P0[0] bidirectional Analog column mux input on GPIO port 0 bit 0.
25 P0[2] bidirectional Analog column mux input and column output on GPIO port 0 bit 2.
26 P0[4] bidirectional Analog column mux input and column output on GPIO port 0 bit 4.
27 P0[6] bidirectional Analog column mux input on GPIO port 0 bit 6.
28 VDD power_in Supply voltage; the datasheet specifies VDD from 3.00 V to 5.25 V.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package SSOP-28-208mil
Category Embedded Processors & Controllers
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature TSTG -55 25 100 °C 19
Ambient temperature with power applied TA -40 85 °C Ambient temperature with power applied 19
Supply voltage on VDD relative to Vss VDD -0.5 6 V Supply voltage on VDD relative to Vss 19
Maximum current into any port pin IMIO -25 50 mA Maximum current into any port pin 19
Maximum current into any port pin configured as analog driver IMAIO -50 50 mA Maximum current into any port pin configured as analog driver 19
Electrostatic discharge voltage ESD 2000 V Human body model ESD. 19
Latch-up current LU 200 mA 19
Ambient temperature TA -40 85 °C 20
Junction temperature TJ -40 100 °C 20
Supply voltage VDD 3 5.25 V 20
Supply current IDD 5 8 mA VDD = 5.0 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. 20
Supply current IDD3 3.3 6 mA VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. 20
Sleep (Mode) current with POR, LVD, sleep timer, and WDT ISB 3 6.5 µA Internal slow speed oscillator, VDD = 3.3 V, -40 °C ≤ TA ≤ 55 °C. 20
Sleep (Mode) current with POR, LVD, sleep timer, and WDT at high temperature ISBH 4 25 µA Internal slow speed oscillator, VDD = 3.3 V, 55 °C < TA ≤ 85 °C. 20
Sleep (Mode) current with POR, LVD, sleep timer, WDT, and external crystal ISBXTL 4 7.5 µA Properly loaded, 1 µW max, 32.768 kHz crystal. VDD = 3.3 V, -40 °C ≤ TA ≤ 55 °C. 20
Sleep (Mode) current with POR, LVD, sleep timer, WDT, and external crystal at high temperature ISBXTLH 5 26 µA Properly loaded, 1 µW max, 32.768 kHz crystal. VDD = 3.3 V, 55 °C < TA ≤ 85 °C. 20
Reference voltage (Bandgap) for Silicon A VREF 1.275 1.3 1.325 V Trimmed for appropriate VDD. 20
Reference voltage (Bandgap) for Silicon B VREF 1.28 1.3 1.32 V Trimmed for appropriate VDD. 20
Pull-up resistor RPU 4 5.6 8 k 21
Pull-down resistor RPD 4 5.6 8 k 21
Low output level VOL 0.75 V IOL = 25 mA, VDD = 4.75 to 5.25 V 21
High-level source current IOH 10 mA VOH = VDD, 1.0 V 21
Low-level sink current IOL 25 mA VOL = 0.75 V 21
Input low level VIL 0.8 V VDD = 3.0 to 5.25 21
Input high level VIH 2.1 V VDD = 3.0 to 5.25 21
Capacitive load on pins as input CIN 3.5 10 pF Package and pin dependent. Temp = 25 °C. 21
Capacitive load on pins as output COUT 3.5 10 pF Package and pin dependent. Temp = 25 °C. 21
Input offset voltage (absolute value) VOSOA 1.6 10 mV Power = low, Opamp bias = low 21
Average input offset voltage drift TCVOSOA 4 20 µV/°C 21
Input capacitance (port 0 analog pins) CINOA 4.5 9.5 pF Package and pin dependent. Temp = 25 °C 21
Common mode rejection ratio CMRROA 60 dB Power = low, Opamp bias = high 22
Open loop gain GOLOA 60 dB Power = low, Opamp bias = high 22
Open loop gain GOLOA 80 dB Power = high, Opamp bias = high 22
Low output voltage swing (internal signals) VOLOWOA 0.2 V Power = low, Opamp bias = high 22
Low output voltage swing (internal signals) VOLOWOA 0.5 V Power = high, Opamp bias = high 22
Supply current (including associated AGND buffer) ISOA 150 200 µA Power = low, Opamp bias = low 22
Supply current (including associated AGND buffer) ISOA 300 400 µA Power = low, Opamp bias = high 22
Supply current (including associated AGND buffer) ISOA 600 800 µA Power = medium, Opamp bias = low 22
Supply current (including associated AGND buffer) ISOA 1200 1600 µA Power = medium, Opamp bias = high 22
Supply current (including associated AGND buffer) ISOA 2400 3200 µA Power = high, Opamp bias = low 22
Supply current (including associated AGND buffer) ISOA 4600 6400 µA Power = high, Opamp bias = high 22
Supply voltage rejection ratio PSRROA 60 dB Vss ≤ VIN ≤ (VDD, 2.25) or (VDD, 1.25 V) ≤ VIN ≤ VDD. 22
5 V output voltage VPUMP 5 V 4.75 5 5.25 V Configured as in Note 15. Average, neglecting ripple. SMP trip voltage is set to 5.0 V. 25
3 V output voltage VPUMP 3 V 3 3.25 3.6 V Configured as in Note 15. Average, neglecting ripple. SMP trip voltage is set to 3.25 V. 25
Low power comparator reference voltage range VREFLPC 0.2 V 23
Input hysterisis VH 60 mV 21
Input leakage (absolute value) IIL 1 nA Gross tested to 1 µA. 21
Input leakage current (port 0 analog pins) IEBOA 20 pA Gross tested to 1 µA. 21
Bake temperature TBAKETEMP 125 °C See package label. 19

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC The emulator consists of a base unit that connects to the PC 7

CAD (KiCad official)

  • Symbol: CY8C27443-24PVXIT
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
  • 3D model files: cy8c27443-24pvxit-etched.step / cy8c27443-24pvxit-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c27443-24pvxit.step / cy8c27443-24pvxit.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (69 pp, sha256 e9e6a6d181dc0113, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF