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README

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SN74HC595DR

Texas Instruments · Shift Registers · SOIC-16

SN74HC595DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 QB tri_state Parallel 3-state output B from the storage register. Drives up to 15 LSTTL loads (±6 mA at 5 V). High-impedance when OE is high.
2 QC tri_state Parallel 3-state output C from the storage register. Drives up to 15 LSTTL loads (±6 mA at 5 V). High-impedance when OE is high.
3 QD tri_state Parallel 3-state output D from the storage register. Drives up to 15 LSTTL loads (±6 mA at 5 V). High-impedance when OE is high.
4 QE tri_state Parallel 3-state output E from the storage register. Drives up to 15 LSTTL loads (±6 mA at 5 V). High-impedance when OE is high.
5 QF tri_state Parallel 3-state output F from the storage register. Drives up to 15 LSTTL loads (±6 mA at 5 V). High-impedance when OE is high.
6 QG tri_state Parallel 3-state output G from the storage register. Drives up to 15 LSTTL loads (±6 mA at 5 V). High-impedance when OE is high.
7 QH tri_state Parallel 3-state output H from the storage register. Drives up to 15 LSTTL loads (±6 mA at 5 V). High-impedance when OE is high.
8 GND power_in Ground reference (0 V) for the device.
9 QH' output Serial output from the shift register (not 3-stated). Used for cascading additional SN74HC595 devices - connect to the SER input of the next stage. Reflects the shift-register QH bit.
10 SRCLR input Active-low shift-register clear input. When low, asynchronously clears the 8-bit shift register. Does not affect the storage register.
11 SRCLK input Shift-register clock input. Serial data on SER is shifted into the shift register on the rising edge. Max clock frequency ~25 MHz at 4.5 V.
12 RCLK input Storage-register (latch) clock input. On the rising edge, the shift-register contents are transferred to the 8-bit D-type storage register that drives QA-QH.
13 OE input Active-low output-enable input. When high, parallel outputs QA-QH are placed in the high-impedance state. Does not affect the storage register contents.
14 SER input Serial data input to the shift register. Sampled on the rising edge of SRCLK. Setup time 20 ns at 4.5 V.
15 QA tri_state Parallel 3-state output A from the storage register (LSB of output byte). Drives up to 15 LSTTL loads (±6 mA at 5 V). High-impedance when OE is high.
16 VCC power_in Positive supply voltage input. Operating range 2 V to 6 V (5 V nominal). Bypass locally with a 0.1 µF ceramic capacitor to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • SN74HC595DRD
  • SN74HC595DR
  • SN74HC595DRDW
  • SN74HC595DRDWR
  • SN74HC595DRN
  • SN74HC595DRNE4
  • SN74HC595DRDB
  • SN74HC595DRDBR
  • SN74HC595DRPW
  • SN74HC595DRPWR
  • SN74HC595DRNS
  • SN74HC595DRNSR
  • SN74HC595DRJ
  • SN74HC595DRFK

CAD (KiCad official)

  • Symbol: SN74HC595DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 215816945704e561, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF