component
HMT1050T
Public Made by Adomby adom
GATEMODE CAN Transceivers, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownHMT1050T
GATEMODE · CAN Transceivers · SOP-8
HMT1050T from GATEMODE, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TXD | input | CAN transmit data input, LOW for dominant and HIGH for recessive bus states; VIH is 2.0 V to VCC and VIL is 0 V to 0.8 V, and a dominant-hold on TXD triggers the dominant time-out that disables the driver. |
| 2 | GND | power_in | Device ground. |
| 3 | VCC | power_in | Transceiver 5-V supply, recommended 4.5 V to 5.5 V, with an absolute maximum of -0.3 V to 7 V. |
| 4 | RXD | output | CAN receive data output, LOW for dominant and HIGH for recessive bus states. |
| 5 | Vref | power_in | Reference output voltage of approximately VCC/2 (0.4VCC to 0.6VCC at -50 µA < IO < 50 µA) for the common-mode point of a split termination; it may be left floating if unused. |
| 6 | CANL | bidirectional | Low-level CAN bus line; bus terminals are rated -50 V to 50 V absolute maximum, with transients to ±200 V per ISO 7637. |
| 7 | CANH | bidirectional | High-level CAN bus line; bus terminals are rated -50 V to 50 V absolute maximum, with transients to ±200 V per ISO 7637. |
| 8 | S | input | Mode-select pin: logic LOW selects high-speed normal mode and logic HIGH selects listen-only silent mode, with VIH of 2.0 V to VCC. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GATEMODE |
| Package | SOP-8 |
| Category | Interface |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.3 | 7 | V | 2 | ||
| Voltage at any bus terminal (CANH, CANL, Vref) | -50 | 50 | V | 2 | |||
| Voltage input, transient pulse (CANH, CANL) | VI | -200 | 200 | V | ISO 7637 test pulses 1, 2, 3a, 3b, 5, 6, 7 | 2 | |
| Voltage input range (TXD, S) | VI | -0.5 | 6 | V | 2 | ||
| Junction temperature | TJ | -55 | 170 | °C | 2 | ||
| Supply voltage | VCC | 4.5 | 5.5 | V | 3 | ||
| Voltage at any bus terminal (separately or common mode) | VI or VIC | -24 | 24 | V | 3 | ||
| High-level input voltage | VIH | 2 | V | TXD, S; printed max is VCC (not numeric) | 3 | ||
| Low-level input voltage | VIL | 0 | 0.8 | V | 3 | ||
| Differential input voltage | VID | -7 | 7 | V | 3 | ||
| High-level output current, driver | IOH | -70 | mA | Driver | 3 | ||
| High-level output current, receiver | IOH | -6 | mA | Receiver | 3 | ||
| Low-level output current, driver | IOL | 70 | mA | Driver | 3 | ||
| Low-level output current, receiver | IOL | 6 | mA | Receiver | 3 | ||
| Junction temperature | TJ | -40 | 150 | °C | 1-Mbps minimum signaling rate with RL = 54Ω | 3 | |
| Bus output voltage (Dominant), CANH | VO(D) | 3 | 3.6 | 4.5 | V | VI = 0V, S at 0V, RL = 60 Ω, 4.75V < VCC < 5.25V | 3 |
| Bus output voltage (Dominant), CANH | VO(D) | 2.75 | 5.2 | V | VI = 0V, S at 0V, RL = 60 Ω, 4.5V < VCC < 5.5V | 3 | |
| Bus output voltage (Dominant), CANL | VO(D) | 0.8 | 1.4 | 1.6 | V | VI = 0V, S at 0V, RL = 60 Ω, 4.75V < VCC < 5.25V | 3 |
| Bus output voltage (Dominant), CANL | VO(D) | 1.6 | V | VI = 0V, S at 0V, RL = 60 Ω, 4.5V < VCC < 5.5V | 3 | ||
| Bus output voltage (Recessive), CANH/CANL | VO(R) | 2 | 2.5 | 3 | V | VI = 3V, S at 0V, RL = 60 Ω, 4.75V < VCC < 5.25V | 3 |
| Bus output voltage (Recessive), CANH/CANL | VO(R) | 1.8 | 2.4 | 3 | V | VI = 3V, S at 0V, RL = 60 Ω, 4.5V < VCC < 5.5V | 3 |
| Differential output voltage (Dominant) | VOD(D) | 1.5 | 2.2 | 3 | V | VI = 0V, RL = 60 Ω, S at 0V, 4.75V < VCC < 5.25V | 3 |
| Differential output voltage (Dominant) | VOD(D) | 1.4 | 3 | V | VI = 0V, RL = 60 Ω, S at 0V, 4.5V < VCC < 5.5V | 3 | |
| Differential output voltage (Dominant), RL = 45 Ω | VOD(D) | 1.4 | 3 | V | VI = 0V, RL = 45 Ω, S at 0V, 4.75V < VCC < 5.25V | 3 | |
| Differential output voltage (Dominant), RL = 45 Ω | VOD(D) | 1.3 | 3 | V | VI = 0V, RL = 45 Ω, S at 0V, 4.5V < VCC < 5.5V | 3 | |
| Differential output voltage (Recessive) | VOD(R) | -0.012 | 0.012 | V | VI = 3V, S at 0V, See Figure 1 and Figure 2 | 3 | |
| Differential output voltage (Recessive), no load | VOD(R) | -0.5 | 0.05 | V | VI = 3V, S at 0V, No Load | 3 | |
| Steady state common-mode output voltage | VOC(SS) | 2 | 2.5 | 3 | V | S at 0V, 4.75V < VCC < 5.25V | 4 |
| Steady state common-mode output voltage | VOC(SS) | 1.9 | 3 | V | S at 0V, 4.5V < VCC < 5.5V | 4 | |
| High-level input current, TXD input | IIH | -2 | 0 | 2 | μA | VI at VCC | 4 |
| Low-level input current, TXD input | IIL | -50 | -30 | -10 | μA | VI at 0V | 4 |
| Short-circuit steady-state output current, CANH | IOS(SS) | -130 | -100 | mA | VCANH = -12V, CANL Open | 4 | |
| Short-circuit steady-state output current, CANL | IOS(SS) | 77 | 105 | mA | VCANL = 12V, CANH Open | 4 | |
| Positive-going input threshold voltage | VIT+ | 800 | 900 | mV | S at 0V | 4 | |
| Negative-going input threshold voltage | VIT- | 500 | 650 | mV | 4 | ||
| Hysteresis voltage (VIT+ - VIT-) | Vhys | 100 | 125 | mV | 4 | ||
| High-level output voltage | VOH | 4 | 4.6 | V | IO = -2mA, See Figure 6, 4.75V < VCC < 5.25V | 4 | |
| High-level output voltage | VOH | 3.8 | V | IO = -2mA, See Figure 6, 4.5V < VCC < 5.5V | 4 | ||
| Low-level output voltage | VOL | 0.3 | 0.4 | V | IO = 2mA, See Figure 6 | 4 | |
| Power-off bus input current | II(off) | 165 | 250 | μA | CANH or CANL = 5V, Other pin at 0V, VCC at 0V, TXD at 0V | 4 | |
| Differential input resistance | RID | 30 | 50 | 80 | kΩ | TXD at 3V, S at 0V | 4 |
| Input resistance (CANH or CANL) | RIN | 15 | 25 | 40 | kΩ | 4 | |
| Input resistance matching | RI(m) | -3 | 0 | 3 | % | V(CANH) = V(CANL) | 4 |
| Total loop delay, driver input to receiver output, Recessive to Dominant | Td(LOOP1) | 70 | 100 | 190 | ns | S at 0V, 4.75V < VCC < 5.25V | 4 |
| Total loop delay, driver input to receiver output, Recessive to Dominant | Td(LOOP1) | 75 | 115 | ns | S at 0V, 4.5V < VCC < 5.5V | 4 | |
| Total loop delay, driver input to receiver output, Dominant to Recessive | Td(LOOP2) | 70 | 110 | 190 | ns | 4.75V < VCC < 5.25V | 4 |
| Total loop delay, driver input to receiver output, Dominant to Recessive | Td(LOOP2) | 75 | 155 | ns | 4.5V < VCC < 5.5V | 4 | |
| Propagation delay time, low-to-high-level output (driver) | tPLH | 25 | 55 | 110 | ns | S at 0V, See Figure 4 | 5 |
| Propagation delay time, high-to-low-level output (driver) | tPHL | 25 | 50 | 90 | ns | 5 | |
| Dominant time-out | T(dom) | 300 | 550 | 700 | μs | VI ↓; 4.75V < VCC < 5.25V | 5 |
| Dominant time-out | T(dom) | 280 | 700 | μs | VI ↓; 4.5V < VCC < 5.5V | 5 | |
| Propagation delay time, low-to-high-level output (receiver) | TPLH | 50 | 75 | 130 | ns | S at 0V or VCC, See Figure 6, 4.75V < VCC < 5.25V | 5 |
| Propagation delay time, low-to-high-level output (receiver) | TPLH | 55 | 135 | ns | S at 0V or VCC, See Figure 6, 4.5V < VCC < 5.5V | 5 | |
| Propagation delay time, high-to-low-level output (receiver) | TPHL | 25 | 50 | 90 | ns | 4.75V < VCC < 5.25V | 5 |
| Propagation delay time, high-to-low-level output (receiver) | TPHL | 30 | 95 | ns | 4.5V < VCC < 5.5V | 5 | |
| 5-V supply current, silent mode | ICC | 2.5 | 5 | mA | Silent mode, S at VCC, VI = VCC | 5 | |
| 5-V supply current, dominant | ICC | 50 | 70 | mA | VI = 0V, 60 Ω Load, S at 0V, 4.75V < VCC < 5.25V | 5 | |
| 5-V supply current, dominant | ICC | 75 | mA | VI = 0V, 60 Ω Load, S at 0V, 4.5V < VCC < 5.5V | 5 | ||
| 5-V supply current, recessive | ICC | 2.5 | 5 | mA | VI = VCC, No Load, S at 0V | 5 | |
| High level input current, S pin | IIH | 20 | 35 | 50 | μA | S at 2V | 5 |
CAD (KiCad official)
- Symbol:
HMT1050T - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
hmt1050t-etched.step/hmt1050t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hmt1050t.step/hmt1050t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GATEMODE datasheet (14 pp, sha256
10b965c5300692f2, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).