component
A5975DTR
Public Made by Adomby adom
STMicroelectronics DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownA5975DTR
STMicroelectronics · DC-DC Converters · SOP-8-EP
A5975DTR from STMicroelectronics, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulator output, rated for a DC voltage of -1 to 40 V and a peak of -5 to 40 V at Δt = 0.1 µs. |
| 2 | SYNCH | input | Master/slave synchronization pin with an absolute voltage range of -0.3 to 4 V. |
| 3 | INH | input | Active-high logic input that disables the device (device OFF above 2.2 V, ON below 0.8 V); it must be grounded if unused, and an internal pull-up disables the device when it is open. |
| 4 | COMP | passive | Error amplifier output used for frequency compensation of the control loop. |
| 5 | FB | input | Feedback input; connecting it directly to the output sets 1.23 V, and an external resistive divider is required for higher output voltages. |
| 6 | VREF | power_out | 3.3 V reference voltage output, which requires no capacitor for stability. |
| 7 | GND | power_in | Ground reference pin; the exposed pad must also be connected to an extended ground plane to reduce thermal resistance. |
| 8 | VCC | power_in | Unregulated DC input voltage with an operating range of 4 V to 36 V and an absolute maximum of 40 V. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | V8 | 40 | V | 7 | |||
| OUT pin DC voltage | V1 | -1 | 40 | V | 7 | ||
| OUT pin peak voltage | V1 | -5 | 40 | V | Δt = 0.1 μs | 7 | |
| Analog pins | V4, V5 | 4 | V | 7 | |||
| INH voltage | V3 | -0.3 | V | upper limit printed as VCC | 7 | ||
| SYNCH voltage | V2 | -0.3 | 4 | V | 7 | ||
| Power dissipation | PTOT | 2.25 | W | TA ≤ 60 °C | 7 | ||
| Operating junction temperature range | TJ | -40 | 150 | °C | 7 | ||
| Storage temperature range | TSTG | -55 | 150 | °C | 7 | ||
| Maximum thermal resistance junction-ambient | RTHJ-A | 40 | °C/W | Package mounted on demonstration board | 7 | ||
| Operating input voltage range | VCC | 4 | 36 | V | V0 = 1.235 V; I0 = 2 A | 8 | |
| MOSFET on-resistance | RDS(on) | 0.25 | 0.5 | Ω | 8 | ||
| Maximum limiting current | IL | 3.75 | 4.5 | 5.25 | A | VCC = 5 V | 8 |
| Switching frequency | fSW | 212 | 250 | 280 | kHz | 8 | |
| Duty cycle | 0 | 100 | % | 8 | |||
| Voltage feedback | V5 | 1.198 | 1.235 | 1.272 | V | 4.4 V < VCC < 36 V, 20 mA < I0 < 2 A | 8 |
| Total operating quiescent current | Iqop | 3 | 5 | mA | 8 | ||
| Quiescent current | Iq | 2.5 | mA | Duty cycle = 0; VFB = 1.5 V | 8 | ||
| Total standby quiescent current | Iqst-by | 50 | 100 | μA | VINH > 2.2 V | 8 | |
| INH threshold voltage | 0.8 | V | Device ON | 8 | |||
| INH threshold voltage | 2.2 | V | Device OFF | 8 | |||
| High level output voltage | VOH | 3.5 | V | VFB = 1 V | 8 | ||
| Low level output voltage | VOL | 0.4 | V | VFB = 1.5 V | 8 | ||
| Source output current | Io source | 190 | 300 | μA | VCOMP = 1.9 V; VFB = 1 V | 8 | |
| Sink output current | Io sink | 1 | 1.5 | mA | VCOMP = 1.9 V; VFB = 1.5 V | 8 | |
| Source bias current | Ib | 2.5 | 4 | μA | 8 | ||
| DC open loop gain | 50 | 65 | dB | RL = ∞ | 8 | ||
| Transconductance | gm | 2.3 | mS | ICOMP = -0.1 mA to 0.1 mA; VCOMP = 1.9 V | 8 | ||
| High input voltage | 2.5 | V | VCC = 4.4 to 36 V; upper limit printed as VREF | 9 | |||
| Low input voltage | 0.74 | V | VCC = 4.4 to 36 V | 9 | |||
| Slave synch current | 0.11 | 0.25 | mA | Vsynch = 0.74 V | 9 | ||
| Slave synch current | 0.21 | 0.45 | mA | Vsynch = 2.33 V | 9 | ||
| Master output amplitude | 2.75 | 3 | V | Isource = 3 mA | 9 | ||
| Output pulse width | 0.2 | 0.35 | μs | No load, Vsynch = 1.65 V | 9 | ||
| Reference voltage | 3.2 | 3.3 | 3.399 | V | IREF = 0 to 5 mA; VCC = 4.4 V to 36 V | 9 | |
| Line regulation | 5 | 10 | mV | IREF = 0 mA; VCC = 4.4 V to 36 V | 9 | ||
| Load regulation | 8 | 15 | mV | IREF = 0 mA | 9 | ||
| Short-circuit current | 5 | 18 | 35 | mA | 9 |
CAD (KiCad official)
- Symbol:
A5975DTR - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
a5975dtr-etched.step/a5975dtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a5975dtr.step/a5975dtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (50 pp, sha256
137db828adf7e7f8, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).