component
π141M30
Public Made by Adomby adom
2Pai Semi Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownπ141M30
2Pai Semi · Digital Isolators · SOIC-16
π141M30 from 2Pai Semi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, 3 V to 5.5 V operating range, bypass with 0.1 µF to 10 µF to GND1. |
| 2 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 3 | VIA | input | Logic input A on side 1. |
| 4 | VIB | input | Logic input B on side 1. |
| 5 | VIC | input | Logic input C on side 1. |
| 6 | VOD | output | Logic output D on side 1 (reverse channel). |
| 7 | NC | unconnected | No connect for the π141M3x variant (this pin is EN1 output enable only on π141M6x). |
| 8 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 9 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 10 | NC | unconnected | No connect for the π141M3x variant (this pin is EN2 output enable only on π141M6x). |
| 11 | VID | input | Logic input D on side 2 (reverse channel). |
| 12 | VOC | output | Logic output C on side 2. |
| 13 | VOB | output | Logic output B on side 2. |
| 14 | VOA | output | Logic output A on side 2. |
| 15 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 16 | VDD2 | power_in | Supply voltage for isolator side 2, 3 V to 5.5 V operating range, bypass with 0.1 µF to 10 µF to GND2. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-16 |
| Category | Interface ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDDx | -0.5 | 7 | V | VDD1-GND1, VDD2-GND2, TA=25°C | 3 | |
| Average Output Current per Pin, Side 1 | IO1 | -10 | 10 | mA | 3 | ||
| Average Output Current per Pin, Side 2 | IO2 | -10 | 10 | mA | 3 | ||
| Common-Mode Transients Immunity | -150 | 150 | kV/µs | 3 | |||
| Storage Temperature | TST | -65 | 150 | °C | 3 | ||
| Ambient Operating Temperature (abs max table) | TA | -40 | 125 | °C | 3 | ||
| Supply Voltage | VDDx | 3 | 5.5 | V | 4 | ||
| High Level Output Current | IOH | -6 | mA | 4 | |||
| Low Level Output Current | IOL | 6 | mA | 4 | |||
| Data Rate | 0 | 10 | Mbps | 4 | |||
| Junction Temperature | TJ | -40 | 150 | °C | 4 | ||
| Ambient Operating Temperature | TA | -40 | 125 | °C | 4 | ||
| Minimum Pulse Width | PW | 100 | ns | Within pulse width distortion (PWD) limit | 5 | ||
| Maximum Data Rate | 10 | Mbps | Within PWD limit | 5 | |||
| Propagation Delay Time | tpHL, tpLH | 5.5 | 8 | 12.5 | ns | 50% input to 50% output @ 5VDC supply | 5 |
| Propagation Delay Time | tpHL, tpLH | 6.5 | 9 | 13.5 | ns | @ 3.3VDC supply | 5 |
| Pulse Width Distortion | PWD | 0 | 0.3 | 0.8 | ns | /tpHL - tpLH/ @ 5VDC supply | 5 |
| Part to Part Propagation Delay Skew | tPSK | 1 | ns | @ 5VDC supply | 5 | ||
| Channel to Channel Propagation Delay Skew | tCSK | 0 | 1 | ns | @ 5VDC supply | 5 | |
| Channel to Channel Propagation Delay Skew | tCSK | 0 | 0.8 | ns | @ 3.3VDC supply | 5 | |
| Output Signal Rise/Fall Time | tr/tf | 1.5 | ns | 10% to 90% signal terminated 50, See figure15 | 5 | ||
| ESD (HBM) | ESD | -8 | 8 | kV | All pins | 5 | |
| Input Current per Signal Channel | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ Signal voltage ≤ VDDX | 6 |
| VDDx Undervoltage Rising Threshold | VDDxUV+ | 2.45 | 2.65 | 2.9 | V | 6 | |
| VDDx Undervoltage Falling Threshold | VDDxUV− | 2.3 | 2.5 | 2.75 | V | 6 | |
| IDD1 Quiescent Supply Current (π141Mxx) | IDD1 (Q) | 483 | 604 | 785 | µA | @ 5VDC supply, 0V Input signal | 6 |
| IDD2 Quiescent Supply Current (π141Mxx) | IDD2 (Q) | 1200 | 1500 | 1950 | µA | @ 5VDC supply, 0V Input signal | 6 |
| IDD1 Quiescent Supply Current (π141Mxx) | IDD1 (Q) | 594 | 742 | 965 | µA | @ 5VDC supply, 5V Input signal | 6 |
| IDD2 Quiescent Supply Current (π141Mxx) | IDD2 (Q) | 1174 | 1468 | 1908 | µA | @ 5VDC supply, 5V Input signal | 6 |
| IDD1 Quiescent Supply Current (π141Mxx) | IDD1 (Q) | 478 | 597 | 776 | µA | @ 3.3VDC supply, 0V Input signal | 6 |
| IDD2 Quiescent Supply Current (π141Mxx) | IDD2 (Q) | 1186 | 1483 | 1928 | µA | @ 3.3VDC supply, 0V Input signal | 6 |
| IDD1 Quiescent Supply Current (π141Mxx) | IDD1 (Q) | 524 | 655 | 852 | µA | @ 3.3VDC supply, 3.3V Input signal | 6 |
| IDD2 Quiescent Supply Current (π141Mxx) | IDD2 (Q) | 1117 | 1396 | 1815 | µA | @ 3.3VDC supply, 3.3V Input signal | 6 |
| IDD1 Supply Current, 1 Mbps (π141Mxx) | IDD1 | 0.73 | 1.1 | mA | @5VDC, 1 Mbps, CL = 0 pF | 7 | |
| IDD2 Supply Current, 1 Mbps (π141Mxx) | IDD2 | 1.6 | 2.4 | mA | @5VDC, 1 Mbps, CL = 0 pF | 7 | |
| IDD1 Supply Current, 10 Mbps (π141Mxx) | IDD1 | 1.21 | 1.82 | mA | @5VDC, 10 Mbps, CL = 0 pF | 7 | |
| IDD2 Supply Current, 10 Mbps (π141Mxx) | IDD2 | 2.73 | 4.1 | mA | @5VDC, 10 Mbps, CL = 0 pF | 7 | |
| IDD1 Supply Current, 1 Mbps (π141Mxx) | IDD1 | 0.66 | 0.99 | mA | @3.3VDC, 1 Mbps, CL = 0 pF | 7 | |
| IDD2 Supply Current, 1 Mbps (π141Mxx) | IDD2 | 1.51 | 2.27 | mA | @3.3VDC, 1 Mbps, CL = 0 pF | 7 | |
| IDD1 Supply Current, 10 Mbps (π141Mxx) | IDD1 | 0.95 | 1.43 | mA | @3.3VDC, 10 Mbps, CL = 0 pF | 7 | |
| IDD2 Supply Current, 10 Mbps (π141Mxx) | IDD2 | 2.2 | 3.3 | mA | @3.3VDC, 10 Mbps, CL = 0 pF | 7 | |
| Dynamic Input Supply Current per Channel | IDDI (D) | 9 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 5VDC Supply | 5 | ||
| Dynamic Output Supply Current per Channel | IDDO (D) | 38 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 5VDC Supply | 5 | ||
| Dynamic Input Supply Current per Channel | IDDI (D) | 5 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 3.3VDC Supply | 5 | ||
| Dynamic Output Supply Current per Channel | IDDO (D) | 23 | µA/Mbps | Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 3.3VDC Supply | 5 | ||
| Common-Mode Transient Immunity | CMTI | 75 | kV/µs | VIN = VDDx or 0V, VCM = 1000 V | 5 | ||
| Jitter (peak-to-peak) | 120 | ps p-p | See the Jitter Measurement section | 5 | |||
| Jitter (rms) | 20 | ps rms | See the Jitter Measurement section | 5 | |||
| VDDx Hysteresis | VDDxUVH | 0.15 | V | 6 | |||
| Rated Dielectric Insulation Voltage | 3000 | V rms | π14xM3x, 1-minute duration | 7 | |||
| Minimum External Air Gap (Clearance) | L (CLR) | 4 | mm | π14xM3x, input terminals to output terminals, shortest distance through air | 7 | ||
| Minimum External Tracking (Creepage) | L (CRP) | 4 | mm | π14xM3x, shortest distance path along body | 7 | ||
| Minimum Internal Gap | 11 | µm | π14xM3x, insulation distance through insulation | 7 | |||
| Capacitance (Input to Output) | CI-O | 0.6 | pF | @1MHz | 7 | ||
| Input Capacitance | CI | 3 | pF | @1MHz | 7 | ||
| IC Junction to Ambient Thermal Resistance | θJA | 100 | °C/W | π14xM3x, thermocouple located at center of package underside | 7 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN V VDE V 0884-10, each π140M3x/π141M3x/π142M3x is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec (partial discharge detection limit = 5 pC); each π14 | 8 |
CAD (KiCad official)
- Symbol:
π141M30 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
141m30-etched.step/141m30-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);141m30.step/141m30.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 2Pai Semi datasheet (17 pp, sha256
ba23ef977116e6fa, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).