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SN74ALVCH16841DLR

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Texas Instruments Latches, SSOP-56-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74ALVCH16841DLR

Texas Instruments · Latches · SSOP-56-300mil

SN74ALVCH16841DLR from Texas Instruments, in a SSOP-56-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-low buffered output enable for the 1Q outputs; a high level places outputs 1Q1 to 1Q10 in the high-impedance state and does not affect latch operation.
2 1Q1 tri_state 3-state true data output of latch 1, bit 1; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
3 1Q2 tri_state 3-state true data output of latch 1, bit 2; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
4 GND power_in Ground reference.
5 1Q3 tri_state 3-state true data output of latch 1, bit 3; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
6 1Q4 tri_state 3-state true data output of latch 1, bit 4; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
7 VCC power_in Supply voltage; 1.65 V to 3.6 V recommended operating range.
8 1Q5 tri_state 3-state true data output of latch 1, bit 5; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
9 1Q6 tri_state 3-state true data output of latch 1, bit 6; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
10 1Q7 tri_state 3-state true data output of latch 1, bit 7; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
11 GND power_in Ground reference.
12 1Q8 tri_state 3-state true data output of latch 1, bit 8; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
13 1Q9 tri_state 3-state true data output of latch 1, bit 9; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
14 1Q10 tri_state 3-state true data output of latch 1, bit 10; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
15 2Q1 tri_state 3-state true data output of latch 2, bit 1; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
16 2Q2 tri_state 3-state true data output of latch 2, bit 2; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
17 2Q3 tri_state 3-state true data output of latch 2, bit 3; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
18 GND power_in Ground reference.
19 2Q4 tri_state 3-state true data output of latch 2, bit 4; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
20 2Q5 tri_state 3-state true data output of latch 2, bit 5; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
21 2Q6 tri_state 3-state true data output of latch 2, bit 6; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
22 VCC power_in Supply voltage; 1.65 V to 3.6 V recommended operating range.
23 2Q7 tri_state 3-state true data output of latch 2, bit 7; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
24 2Q8 tri_state 3-state true data output of latch 2, bit 8; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
25 GND power_in Ground reference.
26 2Q9 tri_state 3-state true data output of latch 2, bit 9; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
27 2Q10 tri_state 3-state true data output of latch 2, bit 10; rated IOH -24 mA and IOL 24 mA at VCC = 3 V.
28 2OE input Active-low buffered output enable for the 2Q outputs; a high level places outputs 2Q1 to 2Q10 in the high-impedance state and does not affect latch operation.
29 2LE input Latch enable for latch group 2; Q outputs follow D while high and are latched when taken low.
30 2D10 input Noninverting data input of latch 2, bit 10, with active bus hold; input must remain between 0 V and VCC.
31 2D9 input Noninverting data input of latch 2, bit 9, with active bus hold; input must remain between 0 V and VCC.
32 GND power_in Ground reference.
33 2D8 input Noninverting data input of latch 2, bit 8, with active bus hold; input must remain between 0 V and VCC.
34 2D7 input Noninverting data input of latch 2, bit 7, with active bus hold; input must remain between 0 V and VCC.
35 VCC power_in Supply voltage; 1.65 V to 3.6 V recommended operating range.
36 2D6 input Noninverting data input of latch 2, bit 6, with active bus hold; input must remain between 0 V and VCC.
37 2D5 input Noninverting data input of latch 2, bit 5, with active bus hold; input must remain between 0 V and VCC.
38 2D4 input Noninverting data input of latch 2, bit 4, with active bus hold; input must remain between 0 V and VCC.
39 GND power_in Ground reference.
40 2D3 input Noninverting data input of latch 2, bit 3, with active bus hold; input must remain between 0 V and VCC.
41 2D2 input Noninverting data input of latch 2, bit 2, with active bus hold; input must remain between 0 V and VCC.
42 2D1 input Noninverting data input of latch 2, bit 1, with active bus hold; input must remain between 0 V and VCC.
43 1D10 input Noninverting data input of latch 1, bit 10, with active bus hold; input must remain between 0 V and VCC.
44 1D9 input Noninverting data input of latch 1, bit 9, with active bus hold; input must remain between 0 V and VCC.
45 1D8 input Noninverting data input of latch 1, bit 8, with active bus hold; input must remain between 0 V and VCC.
46 GND power_in Ground reference.
47 1D7 input Noninverting data input of latch 1, bit 7, with active bus hold; input must remain between 0 V and VCC.
48 1D6 input Noninverting data input of latch 1, bit 6, with active bus hold; input must remain between 0 V and VCC.
49 1D5 input Noninverting data input of latch 1, bit 5, with active bus hold; input must remain between 0 V and VCC.
50 VCC power_in Supply voltage; 1.65 V to 3.6 V recommended operating range.
51 1D4 input Noninverting data input of latch 1, bit 4, with active bus hold; input must remain between 0 V and VCC.
52 1D3 input Noninverting data input of latch 1, bit 3, with active bus hold; input must remain between 0 V and VCC.
53 GND power_in Ground reference.
54 1D2 input Noninverting data input of latch 1, bit 2, with active bus hold; input must remain between 0 V and VCC.
55 1D1 input Noninverting data input of latch 1, bit 1, with active bus hold; input must remain between 0 V and VCC.
56 1LE input Latch enable for latch group 1; Q outputs follow D while high and are latched when taken low.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-56-300mil
Category Logic
Pins 56

CAD (KiCad official)

  • Symbol: SN74ALVCH16841DLR
  • Footprint: Package_SO:SSOP-56_7.5x18.5mm_P0.635mm
  • 3D model: SSOP-56-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74alvch16841dlr-etched.step / sn74alvch16841dlr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74alvch16841dlr.step / sn74alvch16841dlr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (19 pp, sha256 0ca1eefeed0667c3, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF