component
CD4017SA.TB
Public Made by Adomby adom
Wuxi I-core Elec Counters / Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownCD4017SA.TB
Wuxi I-core Elec · Counters / Dividers · SOP-16
CD4017SA.TB from Wuxi I-core Elec, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q5 | output | Decoded output (active HIGH) for counter state 5. |
| 2 | Q1 | output | Decoded output (active HIGH) for counter state 1. |
| 3 | Q0 | output | Decoded output (active HIGH) for counter state 0; HIGH when MR is HIGH. |
| 4 | Q2 | output | Decoded output (active HIGH) for counter state 2. |
| 5 | Q6 | output | Decoded output (active HIGH) for counter state 6. |
| 6 | Q7 | output | Decoded output (active HIGH) for counter state 7. |
| 7 | Q3 | output | Decoded output (active HIGH) for counter state 3. |
| 8 | VSS | power_in | Ground (0V). |
| 9 | Q8 | output | Decoded output (active HIGH) for counter state 8. |
| 10 | Q4 | output | Decoded output (active HIGH) for counter state 4. |
| 11 | Q9 | output | Decoded output (active HIGH) for counter state 9. |
| 12 | Q5-9 | output | Carry output, active LOW while counter is in states 5 to 9; can drive CP0 of the next cascaded counter. |
| 13 | CP1 | input | Clock input (HIGH-to-LOW edge-triggered, active LOW clock); advances counter on falling edge while CP0 is HIGH. |
| 14 | CP0 | input | Clock input (LOW-to-HIGH edge-triggered); advances counter on rising edge while CP1 is LOW. |
| 15 | MR | input | Master reset input (asynchronous, active HIGH); resets counter to zero (Q0=HIGH, Q1 to Q9=LOW) independent of clocks. |
| 16 | VDD | power_in | Supply voltage, recommended range 3V to 15V referenced to VSS (absolute max +18V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I-core Elec |
| Package | SOP-16 |
| Category | Logic ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | -0.5 | 18 | V | referenced to VSS | 7 | |
| DC input current | IIK | 10 | mA | any one input (±10) | 7 | ||
| Storage temperature | Tstg | -65 | 150 | ℃ | 7 | ||
| Total power dissipation | Ptot | 500 | mW | SOP16 derates 8mW/K above 70℃ | 7 | ||
| Device dissipation | P | 100 | mW | per output transistor | 7 | ||
| Soldering temperature | TL | 250 | ℃ | 10s, SOP | 7 | ||
| Supply voltage | VDD | 3 | 15 | V | 7 | ||
| Ambient temperature | Tamb | -40 | 85 | ℃ | in free air | 7 | |
| Clock input frequency | fCL | 2.5 | MHz | VDD=5V | 7 | ||
| Clock input frequency | fCL | 5 | MHz | VDD=10V | 7 | ||
| Clock input frequency | fCL | 5.5 | MHz | VDD=15V | 7 | ||
| Clock pulse width | tw | 200 | ns | VDD=5V | 7 | ||
| Clock pulse width | tw | 90 | ns | VDD=10V | 7 | ||
| Clock pulse width | tw | 60 | ns | VDD=15V | 7 | ||
| Clock inhibit setup time | ts | 230 | ns | VDD=5V | 7 | ||
| Clock inhibit setup time | ts | 100 | ns | VDD=10V | 7 | ||
| Clock inhibit setup time | ts | 70 | ns | VDD=15V | 7 | ||
| Reset pulse width | tRW | 260 | ns | VDD=5V | 7 | ||
| Reset pulse width | tRW | 110 | ns | VDD=10V | 7 | ||
| Reset pulse width | tRW | 60 | ns | VDD=15V | 7 | ||
| Reset removal time | trec | 400 | ns | VDD=5V | 7 | ||
| Reset removal time | trec | 280 | ns | VDD=10V | 7 | ||
| Reset removal time | trec | 150 | ns | VDD=15V | 7 | ||
| Supply current | IDD | 0.04 | 5 | uA | Tamb=25℃, VIN=0,5, VDD=5V | 8 | |
| Supply current | IDD | 0.04 | 10 | uA | Tamb=25℃, VIN=0,10, VDD=10V | 8 | |
| Supply current | IDD | 0.04 | 20 | uA | Tamb=25℃, VIN=0,15, VDD=15V | 8 | |
| LOW-level output current | IOL | 0.51 | 1 | mA | Tamb=25℃, VO=0.4V, VIN=0,5, VDD=5V | 8 | |
| LOW-level output current | IOL | 1.3 | 2.6 | mA | Tamb=25℃, VO=0.5V, VIN=0,10, VDD=10V | 8 | |
| LOW-level output current | IOL | 3.4 | 6.8 | mA | Tamb=25℃, VO=1.5V, VIN=0,15, VDD=15V | 8 | |
| HIGH-level output current | IOH | -0.51 | -1 | mA | Tamb=25℃, VO=4.6V, VIN=0,5, VDD=5V | 8 | |
| HIGH-level output current | IOH | -1.6 | -3.2 | mA | Tamb=25℃, VO=2.5V, VIN=0,5, VDD=5V | 8 | |
| HIGH-level output current | IOH | -1.3 | -2.6 | mA | Tamb=25℃, VO=9.5V, VIN=0,10, VDD=10V | 8 | |
| HIGH-level output current | IOH | -3.4 | -6.8 | mA | Tamb=25℃, VO=13.5V, VIN=0,15, VDD=15V | 8 | |
| LOW-level output voltage | VOL | 0 | 0.05 | V | Tamb=25℃, VIN=0,5, VDD=5V | 8 | |
| HIGH-level output voltage | VOH | 4.95 | 5 | V | Tamb=25℃, VIN=0,5, VDD=5V | 8 | |
| HIGH-level output voltage | VOH | 9.95 | 10 | V | Tamb=25℃, VIN=0,10, VDD=10V | 8 | |
| HIGH-level output voltage | VOH | 14.95 | 15 | V | Tamb=25℃, VIN=0,15, VDD=15V | 8 | |
| LOW-level input voltage | VIL | 1.5 | V | Tamb=25℃, VO=0.5,4.5V, VDD=5V | 8 | ||
| LOW-level input voltage | VIL | 3 | V | Tamb=25℃, VO=1,9V, VDD=10V | 8 | ||
| LOW-level input voltage | VIL | 4 | V | Tamb=25℃, VO=1.5,13.5V, VDD=15V | 8 | ||
| HIGH-level input voltage | VIH | 3.5 | V | Tamb=25℃, VO=0.5,4.5V, VDD=5V | 8 | ||
| HIGH-level input voltage | VIH | 7 | V | Tamb=25℃, VO=1,9V, VDD=10V | 8 | ||
| HIGH-level input voltage | VIH | 11 | V | Tamb=25℃, VO=1.5,13.5V, VDD=15V | 8 | ||
| Supply current | IDD | 150 | uA | Tamb=+85℃, VIN=0,5, VDD=5V | 8 | ||
| Supply current | IDD | 300 | uA | Tamb=+85℃, VIN=0,10, VDD=10V | 8 | ||
| Supply current | IDD | 600 | uA | Tamb=+85℃, VIN=0,15, VDD=15V | 8 | ||
| Propagation delay CP0, CP1 to Q0-Q9 | tPHL, tPLH | 325 | 650 | ns | VDD=5V; see Figure 7 | 9 | |
| Propagation delay CP0, CP1 to Q0-Q9 | tPHL, tPLH | 135 | 270 | ns | VDD=10V; see Figure 7 | 9 | |
| Propagation delay CP0, CP1 to Q0-Q9 | tPHL, tPLH | 85 | 170 | ns | VDD=15V; see Figure 7 | 9 | |
| Propagation delay MR to Q0-Q9 | tPHL, tPLH | 265 | 530 | ns | VDD=5V; see Figure 7 | 9 | |
| Propagation delay MR to Q0-Q9 | tPHL, tPLH | 115 | 230 | ns | VDD=10V; see Figure 7 | 9 | |
| Propagation delay MR to Q0-Q9 | tPHL, tPLH | 85 | 170 | ns | VDD=15V; see Figure 7 | 9 | |
| Maximum clock frequency | fCL | 2.5 | 5 | MHz | VDD=5V; see Figure 8 | 9 | |
| Maximum clock frequency | fCL | 5 | 10 | MHz | VDD=10V; see Figure 8 | 9 | |
| Maximum clock frequency | fCL | 5.5 | 11 | MHz | VDD=15V; see Figure 8 | 9 | |
| Input capacitance | CI | 5 | pF | any input | 9 |
CAD (KiCad official)
- Symbol:
CD4017SA.TB - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4017sa-tb-etched.step/cd4017sa-tb-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4017sa-tb.step/cd4017sa-tb.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Wuxi I-core Elec datasheet (15 pp, sha256
cc27913b030e2f1b, retrieved 2026-10-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).