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AD7091R-8BCPZ-RL7

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Analog Devices Analog To Digital Converters (ADCs), LFCSP-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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AD7091R-8BCPZ-RL7

Analog Devices · Analog To Digital Converters (ADCs) · LFCSP-24(4x4)

AD7091R-8BCPZ-RL7 from Analog Devices, in a LFCSP-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply input with a 2.7 V to 5.25 V range, to be decoupled to GND.
2 REGCAP passive Decoupling capacitor pin for the internal regulator output, decoupled separately to GND using a 1.0 µF capacitor.
3 REFIN/REFOUT bidirectional 2.5 V reference output, decoupled to GND (typically 2.2 µF), which can be overdriven by an external reference of 1.0 V to VDD.
4 GND power_in Chip ground pin, the ground reference point for all circuitry on the AD7091R-8.
5 MUXOUT output Multiplexer output, tied directly to ADCIN if no external filtering or buffering is required, otherwise to the input of the conditioning network.
6 VIN0 input Analog Input 0, single-ended, with an input range of 0 V to VREF.
7 VIN2 input Analog Input 2, single-ended, with an input range of 0 V to VREF.
8 ALERT/BUSY/GPO0 output Configurable alert output (conversion result outside limits), BUSY output indicating conversion in progress, or general-purpose digital output; open-drain use needs a pull-up to VDRIVE.
9 VIN4 input Analog Input 4, single-ended, with an input range of 0 V to VREF.
10 VIN6 input Analog Input 6, single-ended, with an input range of 0 V to VREF.
11 VIN7 input Analog Input 7, single-ended, with an input range of 0 V to VREF.
12 VIN5 input Analog Input 5, single-ended, with an input range of 0 V to VREF.
13 GPO1 output General-purpose digital output.
14 VIN3 input Analog Input 3, single-ended, with an input range of 0 V to VREF.
15 VIN1 input Analog Input 1, single-ended, with an input range of 0 V to VREF.
16 ADCIN input ADC input giving access to the on-chip track-and-hold, tied to MUXOUT if no external conditioning is needed.
17 GND power_in Chip ground pin, the ground reference point for all circuitry on the AD7091R-8.
18 SDI input Serial data input for writing to on-chip control registers, clocked in on the rising edge of SCLK, MSB first.
19 SDO output Serial data output of the conversion result, clocked out MSB first on the falling edge of SCLK, with 13 SCLKs required to access the data.
20 SCLK input Serial clock input.
21 CONVST input Edge-triggered convert start input; the falling edge places the track-and-hold into hold mode and initiates a conversion.
22 VDRIVE power_in Logic power supply input setting the interface voltage, 1.8 V to 5.25 V, decoupled with typically 10 µF and 0.1 µF to GND.
23 CS input Chip select input; when held low the serial bus is enabled and CS frames the output data on the SPI.
24 RESET input Logic reset input.
25 EPAD passive Exposed pad, not connected internally, recommended to be soldered to GND.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-24(4x4)
Category ADC/DAC/Data Conversion
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Signal-to-Noise Ratio SNR 66.5 70 dB fIN = 10 kHz sine wave 3
Signal-to-Noise-and-Distortion Ratio SINAD 65.5 69 dB fIN = 10 kHz sine wave 3
Integral Nonlinearity INL -1 0.7 1 LSB VDD ≥ 3.0 V 3
Integral Nonlinearity INL -1.25 0.8 1.25 LSB VDD ≥ 2.7 V 3
Differential Nonlinearity DNL -0.9 0.3 0.9 LSB Guaranteed no missing codes to 12 bits 3
Offset Error -1.5 0.2 1.5 mV TA = 25°C 3
Offset Error Matching -1.5 0.2 1.5 mV TA = 25°C 3
Gain Error -0.1 0 0.1 % FS TA = 25°C 3
Gain Error Matching -0.1 0 0.1 % FS TA = 25°C 3
Input Voltage Range 0 V At ADCIN; upper limit printed as VREF 3
DC Leakage Current -1 1 µA 3
Internal Reference Output REFOUT 2.49 2.5 2.51 V Internal reference output, TA = 25°C 3
External Reference Input REFIN 1 V External reference input; upper limit printed as VDD 3
Logic Input Current IIN -1 1 µA Typically 10 nA, VIN = 0 V or VDRIVE 3
Output Low Voltage VOL 0.4 V ISINK = 200 µA 3
Floating State Leakage Current -1 1 µA 3
Total Harmonic Distortion THD -80 dB fIN = 10 kHz sine wave 3
Spurious-Free Dynamic Range SFDR -81 dB fIN = 1 kHz sine wave 3
Channel-to-Channel Isolation -95 dB 3
Aperture Delay 5 ns 3
Aperture Jitter 40 ps 3
Full Power Bandwidth 1.5 MHz At −3 dB 3
Full Power Bandwidth 1.2 MHz At −0.1 dB 3
Resolution 12 Bits 3
Offset Error Drift 2 ppm/°C 3
Gain Error Drift 2 ppm/°C 3
Input Capacitance 10 pF During acquisition phase 3
Input Capacitance 1.5 pF Outside acquisition phase 3
Multiplexer On Resistance 50 Ω VDD = 5.0 V 3
Multiplexer On Resistance 100 Ω VDD = 2.5 V 3
Reference Drift 5 ppm/°C 3
Reference Power-On Time 50 ms CREF = 2.2 µF 3
VDD to GND VDD -0.3 7 V TA = 25°C 7
VDRIVE to GND VDRIVE -0.3 7 V TA = 25°C 7
Digital Input Voltage to GND -0.3 V Upper limit printed as VDRIVE + 0.3 V 7
Digital Output Voltage to GND -0.3 V Upper limit printed as VDRIVE + 0.3 V 7
Analog Input Voltage to GND -0.3 V Upper limit printed as VREF + 0.3 V 7
Input Current to Any Pin Except Supplies -10 10 mA Transient currents of up to 100 mA do not cause SCR latch-up 7
Operating Temperature Range -40 125 °C 7
Storage Temperature Range -65 150 °C 7
Junction Temperature 150 °C 7
ESD Human Body Model HBM 1.5 kV 7
ESD Field Induced Charged Device Model FICDM 500 V 7
Thermal Resistance Junction-to-Ambient θJA 47.3 °C/W 24-Lead LFCSP 7
Thermal Resistance Junction-to-Case θJC 27.78 °C/W 24-Lead LFCSP 7

CAD (KiCad official)

  • Symbol: AD7091R-8BCPZ-RL7
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: LFCSP-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: ad7091r-8bcpz-rl7-etched.step / ad7091r-8bcpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7091r-8bcpz-rl7.step / ad7091r-8bcpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (39 pp, sha256 9c0395b23368e515, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF