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AD2S1210WDSTZRL7

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Analog Devices ADCs/DACs - Special Purpose, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD2S1210WDSTZRL7

Analog Devices · ADCs/DACs - Special Purpose · LQFP-48(7x7)

AD2S1210WDSTZRL7 from Analog Devices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RES1 input Resolution Select 1 logic input that, together with RES0, programs the converter resolution.
2 CS input Active-low chip select logic input; the device is enabled when CS is held low.
3 RD input Edge-triggered logic input that, with SOE high, acts as frame sync and output enable for parallel outputs DB15 to DB0 (enabled when CS and RD are low); hold high when SOE is low.
4 WR/FSYNC input Edge-triggered logic input that, with SOE high, is the input enable for DB7 to DB0 (CS and WR/FSYNC low); with SOE low it is the frame sync and enable for the serial data bus.
5 DGND power_in Digital ground reference; may be tied to the AGND plane and must stay within 0.3 V of AGND even on transients.
6 DVDD power_in Digital supply voltage, 4.75 V to 5.25 V, within 0.3 V of AVDD even on transients.
7 CLKIN input Clock input for a crystal/oscillator or single-ended clock, specified from 6.144 MHz to 10.24 MHz.
8 XTALOUT output Crystal output used with CLKIN; treat as no connect when a single-ended clock source drives CLKIN.
9 SOE input Serial Output Enable logic input: low selects the serial interface, high selects the parallel interface.
10 SAMPLE input Sample Result logic input; a high-to-low transition transfers position and velocity data to their registers and updates the fault register.
11 DB15/SDO tri_state With SOE high, DB15 three-state data output controlled by CS and RD; with SOE low, serial data output clocked out on the rising edge of SCLK.
12 DB14/SDI bidirectional With SOE high, DB14 three-state data output controlled by CS and RD; with SOE low, serial data input clocked in on the falling edge of SCLK.
13 DB13/SCLK bidirectional In parallel mode DB13 three-state data output controlled by CS and RD; in serial mode the serial clock input.
14 DB12 tri_state Data Bit 12, three-state data output controlled by CS and RD.
15 DB11 tri_state Data Bit 11, three-state data output controlled by CS and RD.
16 DB10 tri_state Data Bit 10, three-state data output controlled by CS and RD.
17 DB9 tri_state Data Bit 9, three-state data output controlled by CS and RD.
18 VDRIVE power_in Logic power supply input setting the interface voltage, 2.3 V to 5.25 V, never exceeding AVDD or DVDD by more than 0.3 V; decouple to DGND.
19 DGND power_in Digital ground reference; may be tied to the AGND plane and must stay within 0.3 V of AGND even on transients.
20 DB8 tri_state Data Bit 8, three-state data output controlled by CS and RD.
21 DB7 bidirectional Data Bit 7, three-state data input/output controlled by CS, RD and WR/FSYNC.
22 DB6 bidirectional Data Bit 6, three-state data input/output controlled by CS, RD and WR/FSYNC.
23 DB5 bidirectional Data Bit 5, three-state data input/output controlled by CS, RD and WR/FSYNC.
24 DB4 bidirectional Data Bit 4, three-state data input/output controlled by CS, RD and WR/FSYNC.
25 DB3 bidirectional Data Bit 3, three-state data input/output controlled by CS, RD and WR/FSYNC.
26 DB2 bidirectional Data Bit 2, three-state data input/output controlled by CS, RD and WR/FSYNC.
27 DB1 bidirectional Data Bit 1, three-state data input/output controlled by CS, RD and WR/FSYNC.
28 DB0 bidirectional Data Bit 0, three-state data input/output controlled by CS, RD and WR/FSYNC.
29 A output Incremental encoder emulation output A, free running and valid if the resolver input signals are valid.
30 B output Incremental encoder emulation output B, free running and valid if the resolver input signals are valid.
31 NM output North marker incremental encoder emulation output, free running and valid if the resolver input signals are valid.
32 DIR output Direction logic output for the encoder emulation outputs, high for increasing angular rotation.
33 RESET input Reset logic input; an external signal must hold it low until VDD is within the 4.75 V to 5.25 V operating range.
34 LOT output Loss of Tracking logic output, indicated by a logic low and not latched.
35 DOS output Degradation of Signal logic output, low when a resolver input exceeds the DOS threshold or sine/cosine amplitude mismatch occurs.
36 A1 input Mode Select 1 logic input that, with A0, selects the operating mode.
37 A0 input Mode Select 0 logic input that, with A1, selects the operating mode.
38 EXC output Analog sinusoidal excitation output to the resolver, with frequency programmable via the excitation frequency register.
39 EXC_N output Analog complement excitation output (EXC complement) to the resolver, with frequency programmable via the excitation frequency register.
40 AGND power_in Analog ground reference for analog inputs and external references; must stay within 0.3 V of DGND even on transients.
41 SIN input Positive analog input of the SIN/SINLO differential pair, input range 2.3 V p-p to 4.0 V p-p.
42 SINLO input Negative analog input of the SIN/SINLO differential pair, input range 2.3 V p-p to 4.0 V p-p.
43 AVDD power_in Analog supply voltage, 4.75 V to 5.25 V, within 0.3 V of DVDD even on transients.
44 COSLO input Negative analog input of the COS/COSLO differential pair, input range 2.3 V p-p to 4.0 V p-p.
45 COS input Positive analog input of the COS/COSLO differential pair, input range 2.3 V p-p to 4.0 V p-p.
46 REFBYP passive Reference bypass pin for decoupling capacitors; typical recommended values are 10 µF and 0.01 µF.
47 REFOUT output Voltage reference output.
48 RES0 input Resolution Select 0 logic input that, together with RES1, programs the converter resolution.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-48(7x7)
Category Data Acquisition
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Sine/cosine input voltage amplitude 2.3 3.15 4 V p-p Sinusoidal waveforms, differential SIN to SINLO, COS to COSLO 3
Phase lock range -44 44 Degrees Sine/cosine vs. EXC output, Control Register D3 = 0 3
Common-mode rejection -20 20 arc sec/V 10 Hz to 1 MHz, Control Register D4 = 0 3
Angular accuracy (B, D grades) -2.5 2.5 arc min B, D grades; plus 1 LSB 3
Linearity INL 10-bit INL -1 1 LSB 10-Bit, B, D grades 3
Linearity INL 12-bit INL -2 2 LSB 12-Bit, B, D grades 3
Linearity INL 14-bit INL -4 4 LSB 14-Bit, B, D grades 3
Linearity INL 16-bit INL -16 16 LSB 16-Bit, B, D grades 3
Linearity DNL DNL -0.9 0.9 LSB 3
Repeatability -1 1 LSB 3
Velocity accuracy 10-bit -2 2 LSB 10-Bit, B, D grades, zero acceleration 3
Velocity accuracy 12-bit -2 2 LSB 12-Bit, B, D grades, zero acceleration 3
Velocity accuracy 14-bit -4 4 LSB 14-Bit, B, D grades, zero acceleration 3
Velocity accuracy 16-bit -16 16 LSB 16-Bit, B, D grades, zero acceleration 3
Bandwidth 10-bit 2000 6500 Hz 10-Bit 3
Bandwidth 10-bit 2900 5300 Hz 10-Bit, CLKIN = 8.192 MHz 3
Bandwidth 12-bit 900 2800 Hz 12-Bit 3
Bandwidth 12-bit 1200 2200 Hz 12-Bit, CLKIN = 8.192 MHz 3
Bandwidth 14-bit 400 1500 Hz 14-Bit 3
Bandwidth 14-bit 600 1200 Hz 14-Bit, CLKIN = 8.192 MHz 3
Bandwidth 16-bit 100 350 Hz 16-Bit 3
Bandwidth 16-bit 125 275 Hz 16-Bit, CLKIN = 8.192 MHz 3
Delay SCLK rising edge to DBx valid (t24) t24 24 ns VDRIVE = 4.5 V to 5.25 V 7
Delay SCLK rising edge to DBx valid (t24) t24 18 ns VDRIVE = 2.7 V to 3.6 V 7
Delay SCLK rising edge to DBx valid (t24) t24 32 ns VDRIVE = 2.3 V to 2.7 V 7
SDI setup time prior to SCLK falling edge (t27) t27 3 ns 7
SDI hold time after SCLK falling edge (t28) t28 2 ns 7
Delay WR/FSYNC rising edge to SDO high-Z (t29) t29 15 ns 7
Delay CS falling edge to WR/FSYNC falling edge (t31) t31 2 ns Normal mode 7
A0 and A1 setup time before WR/FSYNC falling edge (t32) t32 2 ns 7
Delay WR/FSYNC rising edge to WR/FSYNC falling edge (t34) t34 10 ns 7
Frequency of SCLK input (fSCLK) fSCLK 20 MHz VDRIVE = 4.5 V to 5.25 V 7
Frequency of SCLK input (fSCLK) fSCLK 25 MHz VDRIVE = 2.7 V to 3.6 V 7
Frequency of SCLK input (fSCLK) fSCLK 15 MHz VDRIVE = 2.3 V to 2.7 V 7
RESET held low after VDD in range (tRST) tRST 10 μs After VDD is within the specified range 31
AVDD to AGND, DGND AVDD -0.3 7 V 8
DVDD to AGND, DGND DVDD -0.3 7 V 8
VDRIVE to AGND, DGND VDRIVE -0.3 V 8
AVDD to DVDD -0.3 0.3 V 8
AGND to DGND -0.3 0.3 V 8
Analog input voltage to AGND -0.3 V 8
Digital input voltage to DGND -0.3 V 8
Digital output voltage to DGND -0.3 V 8
Analog output voltage swing -0.3 V 8
Input current to any pin except supplies -10 10 mA Any pin except supplies 8
Operating temperature range (ambient), C and D grades -40 125 °C C, D grades (ambient) 8
Storage temperature range -65 150 °C 8
ESD HBM 2 kV HBM 8
AVDD analog supply voltage AVDD 4.75 5 5.25 V 9
DVDD digital supply voltage DVDD 4.75 5 5.25 V 9
VDRIVE logic supply voltage VDRIVE 2.3 5.25 V 10
Thermal impedance, junction to ambient θJA 54 °C/W JEDEC 2S2P standard board 8
Thermal impedance, junction to case θJC 15 °C/W 8
RoHS-compliant soldering reflow temperature 260 °C RoHS-compliant temperature, soldering reflow 8

CAD (KiCad official)

  • Symbol: AD2S1210WDSTZRL7
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ad2s1210wdstzrl7-etched.step / ad2s1210wdstzrl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad2s1210wdstzrl7.step / ad2s1210wdstzrl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (34 pp, sha256 7e50f03b4946913f, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF