component
LKS32MC454CCT8
Public Made by Adomby adom
LINKOSEMI Microcontrollers (MCU/MPU/SOC), TQFP-48L(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLKS32MC454CCT8
LINKOSEMI · Microcontrollers (MCU/MPU/SOC) · TQFP-48L(7x7)
LKS32MC454CCT8 from LINKOSEMI, in a TQFP-48L(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0_6/RST_n/5VT | bidirectional | P0.6 general-purpose I/O that serves as the external chip reset input (RST_n); it is 5V-tolerant, accepting 5V input levels, but its maximum output is still 3.3V. |
| 2 | VSS | power_in | Ground reference (GND) for the device. |
| 3 | AVDD | power_in | 3.3V power input; the output of the 5V-to-3.3V LDO requires an external 10uF + 0.1uF capacitor. |
| 4 | P0_10/MCPWM1_CH0P/SPI0_CSN/TIM1_CH1/EFLS_DAT[2]/CMP4_IN/SWDIOTMS/5VT | bidirectional | PWM1 channel 0 high side, SPI0 chip select, Timer1 channel 1, external flash data 2, comparator 4 negative input, and SWD data/JTAG TMS; 5V-tolerant input with 3.3V maximum output. |
| 5 | P0_11/MCPWM1_CH1N/UART1_RXD/SPI0_DI/SCL1/TIM4_CH1/EFLS_DAT[3]/CMP4_IP0/TDI/5VT | bidirectional | PWM1 channel 1 low side, UART1 receive, SPI0 input, I2C1 clock, Timer4 channel 1, external flash data 3, comparator 4 positive input 0, and JTAG TDI; 5V-tolerant input with 3.3V maximum output, and needs SYS_IO_CFG configuration to be used as normal GPIO. |
| 6 | P0_12/MCPWM1_CH1P/UART1_TXD/SPI0_DO/SDA1/TIM4_CH0/CAN_TMR/EFLS_CSN/CMP4_IP1/SWCLKTCLK/5VT | bidirectional | PWM1 channel 1 high side, UART1 send, SPI0 output, I2C1 data, Timer4 channel 0, CAN external timestamp clock, external flash chip select, comparator 4 positive input 1, and SWD clock/JTAG TCLK; 5V-tolerant input with 3.3V maximum output, and needs SYS_IO_CFG configuration to be used as normal GPIO. |
| 7 | P0_13/MCPWM1_CH2N/UART0_TXD/SPI1_CSN/TIM4_CH0/CAN_TX/CMP4_IP2/WAKE4/EXTI6/TDO/5VT | bidirectional | PWM1 channel 2 low side, UART0 send, SPI1 chip select, Timer4 channel 0, CAN send, comparator 4 positive input 2, WAKE4/EXTI6 and JTAG TDO; 5V-tolerant input with 3.3V maximum output, and needs SYS_IO_CFG configuration to be used as normal GPIO. |
| 8 | P0_14/CLK/MCPWM1_CH2P/UART0_RXD/SPI1_DI/SCL0/CAN_RX/CMP4_IP3/EXTI7 | bidirectional | Clock output, PWM1 channel 2 high side, UART0 receive, SPI1 input, I2C0 clock, CAN receive, comparator 4 positive input 3 and EXTI7. |
| 9 | P1_0/MCPWM1_CH3P/UART0_TXD/SPI1_DO/SDA0/TIM0_Z | bidirectional | PWM1 channel 3 high side, UART0 send, SPI1 output, I2C0 data and Timer0 Z-axis signal; needs SYS_IO_CFG configuration to be used as normal GPIO. |
| 10 | P1_5/MCPWM0_CH2N/UART1_RXD/SPI0_DI/SCL1/TIM4_CH1/TIM3_Z/CAN_TX/EXTI9/5VT | bidirectional | PWM0 channel 2 low side, UART1 receive, SPI0 input, I2C1 clock, Timer4 channel 1, Timer3 Z-axis signal, CAN send and EXTI9; 5V-tolerant input with 3.3V maximum output. |
| 11 | P1_6/MCPWM0_CH2P/UART1_TXD/SPI0_DO/SDA1/TIM4_CH0 | bidirectional | PWM0 channel 2 high side, UART1 send, SPI0 output, I2C1 data, Timer4 channel 0 and CAN receive; 5V-tolerant input with 3.3V maximum output. |
| 12 | P1_9/MCPWM0_BKIN0/UART2_TXD/SPI1_DO/SDA0/TIM0_CH1/TIM2_CH0/ADC_TRIGGER2/CAN_TX/5VT/FLT | bidirectional | PWM0 stop signal 0, UART2 send, SPI1 output, I2C0 data, Timer0 channel 1, Timer2 channel 0, ADC trigger debugging signal 2 and CAN send; 5V-tolerant input with 3.3V maximum output. |
| 13 | P1_10/MCPWM0_BKIN1/UART2_RXD/SPI1_DI/SCL0/TIM0_CH0/TIM2_CH1/ADC_TRIGGER1/CAN_RX/5VT/FLT | bidirectional | PWM0 stop signal 1, UART2 receive, SPI1 input, I2C0 clock, Timer0 channel 0, Timer2 channel 1, ADC trigger debugging signal 1 and CAN receive; 5V-tolerant input with 3.3V maximum output. |
| 14 | P1_11/MCPWM0_BKIN2/UART2_TXD/SPI0_DO/SDA0/TIM0_CH1/OPA5_IN/WAKE5/EXTI11 | bidirectional | PWM0 stop signal 2, UART2 send, SPI0 output, I2C0 data, Timer0 channel 1, OPA5 negative input, WAKE5 and EXTI11. |
| 15 | P1_12/MCPWM1_CH3N/UART2_RXD/SPI0_DI/SCL0/TIM1_CH0/OPA5_IP/EXTI12 | bidirectional | PWM1 channel 3 low side, UART2 receive, SPI0 input, I2C0 clock, Timer1 channel 0, OPA5 positive input and EXTI12. |
| 16 | P2_5/MCPWM1_CH0P/UART1_RXD/TIM1_CH0/TIM2_CH1/CAN_TMR/EFLS_CLK | bidirectional | PWM1 channel 0 high side, UART1 receive, Timer1 channel 0, Timer2 channel 1, CAN external timestamp clock and external flash clock. |
| 17 | P2_6/MCPWM1_CH2N/UART1_TXD/TIM1_CH1 | bidirectional | PWM1 channel 2 low side, UART1 send and Timer1 channel 1. |
| 18 | P2_9/MCPWM0_CH2P/SDA0/TIM4_CH1/TIM2_Z/EFLS_DAT[0] | bidirectional | PWM0 channel 2 high side, I2C0 data, Timer4 channel 1, Timer2 Z-axis signal and external flash data 0. |
| 19 | P2_10/MCPWM0_CH1P/SCL0/TIM4_CH0/EFLS_DAT[1] | bidirectional | PWM0 channel 1 high side, I2C0 clock, Timer4 channel 0 and external flash data 1. |
| 20 | P2_11/MCPWM0_CH0P/UART0_RXD/TIM4_CH0/TIM3_CH1/EFLS_DAT[2]/5VT | bidirectional | PWM0 channel 0 high side, UART0 receive, Timer4 channel 0, Timer3 channel 1 and external flash data 2; 5V-tolerant input with 3.3V maximum output. |
| 21 | P2_12/MCPWM0_CH2N/UART0_TXD/TIM4_CH1/TIM3_Z/EFLS_DAT[3]/EXTI18/5VT | bidirectional | PWM0 channel 2 low side, UART0 send, Timer4 channel 1, Timer3 Z-axis signal, external flash data 3 and EXTI18; 5V-tolerant input with 3.3V maximum output. |
| 22 | P2_13/HALL0_IN2/MCPWM0_CH1N/TIM4_CH0/TIM3_CH0/ADC_TRIGGER1/EFLS_CSN | bidirectional | Hall 0 input signal 2, PWM0 channel 1 low side, Timer4 channel 0, Timer3 channel 0, ADC trigger debugging signal 1 and external flash chip select (active low). |
| 23 | P2_14/HALL0_IN1/MCPWM0_CH0N/UART2_TXD/TIM3_CH1/ADC_TRIGGER0/CMP3_IN/WAKE6 | bidirectional | Hall 0 input signal 1, PWM0 channel 0 low side, UART2 send, Timer3 channel 1, ADC trigger debugging signal 0, comparator 3 negative input and WAKE6. |
| 24 | P2_15/CMP3_OUT/HALL0_IN0/MCPWM0_BKIN0/UART2_RXD/TIM1_CH0/EFLS_CLK/CMP3_IP0/EXTI19/5VT | bidirectional | Comparator 3 output, Hall 0 input signal 0, PWM0 stop signal 0, UART2 receive, Timer1 channel 0, external flash clock, comparator 3 positive input 0 and EXTI19; 5V-tolerant input with 3.3V maximum output. |
| 25 | P3_0/HALL1_IN2/MCPWM0_CH2N/TIM3_Z/ADC0_CH14/CMP3_IP1/5VT | bidirectional | Hall 1 input signal 2, PWM0 channel 2 low side, Timer3 Z-axis signal, ADC0 channel 14 and comparator 3 positive input 1; 5V-tolerant input with 3.3V maximum output. |
| 26 | P3_1/HALL1_IN1/MCPWM0_BKIN3/SDA0/TIM0_Z/TIM3_CH0/ADC0_CH13/CMP3_IP2/5VT | bidirectional | Hall 1 input signal 1, PWM0 stop signal 3, I2C0 data, Timer0 Z-axis signal, Timer3 channel 0, ADC0 channel 13 and comparator 3 positive input 2; 5V-tolerant input with 3.3V maximum output. |
| 27 | P3_2/CMP3_OUT/HALL1_IN0/SCL0/TIM0_CH0/TIM3_CH0/EFLS_DAT[0]/CMP3_IP3/WAKE7/EXTI20/5VT | bidirectional | Comparator 3 output, Hall 1 input signal 0, I2C0 clock, Timer0 channel 0, Timer3 channel 0, external flash data 0 and comparator 3 positive input 3; 5V-tolerant input with 3.3V maximum output. |
| 28 | P3_3/CMP2_OUT/SPI0_CSN/TIM0_CH1/EFLS_DAT[1]/ADC1_CH13/CMP2_IP0/EXTI21 | bidirectional | Comparator 2 output, SPI0 chip select, Timer0 channel 1, external flash data 1, ADC1 channel 13, comparator 2 positive input 0 and EXTI21. |
| 29 | P3_4/HALL0_IN0/SPI0_CLK/TIM1_CH1/EFLS_DAT[2]/ADC1_CH12/DAC0_OUT/CMP2_IP1/5VT | bidirectional | Hall 0 input signal 0, SPI0 clock, Timer1 channel 1, external flash data 2, ADC1 channel 12, DAC0 output and comparator 2 positive input 1; 5V-tolerant input with 3.3V maximum output. |
| 30 | P3_5/HALL0_IN1/MCPWM1_BKIN2/UART1_RXD/SPI0_DO/TIM1_CH0/CAN_TMR/EFLS_DAT[3]/ADC1_CH11/CMP2_IP2/5VT | bidirectional | Hall 0 input signal 1, PWM1 stop signal 2, UART1 receive, SPI0 output, Timer1 channel 0, CAN external timestamp clock, external flash data 3, ADC1 channel 11 and comparator 2 positive input 2; 5V-tolerant input with 3.3V maximum output. |
| 31 | P3_6/HALL0_IN2/MCPWM1_BKIN3/UART1_TXD/SPI0_DI/TIM1_CH1/ADC_TRIGGER2/CAN_TX/EFLS_CSN/CMP2_IP3/5VT | bidirectional | Hall 0 input signal 2, PWM1 stop signal 3, UART1 send, SPI0 input, Timer1 channel 1, ADC trigger debugging signal 2, CAN send, external flash chip select (active low) and comparator 2 positive input 3; 5V-tolerant input with 3.3V maximum output. |
| 32 | P3_7/CMP2_OUT/MCPWM1_BKIN0/TIM4_CH1/ADC_TRIGGER1/CAN_RX/OPA3_IN/ADC2_CH11/CMP2_IN/EXTI22 | bidirectional | Comparator 2 output, PWM1 stop signal 0, Timer4 channel 1, ADC trigger debugging signal 1, CAN receive, OPA3 negative input, ADC2 channel 11, comparator 2 negative input and EXTI22. |
| 33 | P3_8/MCPWM1_BKIN1/TIM4_CH0/ADC_TRIGGER0/EFLS_CLK/OPA3_IP/ADC2_CH10/EXTI23 | bidirectional | PWM1 stop signal 1, Timer4 channel 0, ADC trigger debugging signal 0, external flash clock, OPA3 positive input, ADC2 channel 10 and EXTI23. |
| 34 | P3_9/MCPWM0_BKIN0/TIM0_CH1/OPA2_IN/ADC2_CH9 | bidirectional | PWM0 stop signal 0, Timer0 channel 1, OPA2 negative input and ADC2 channel 9. |
| 35 | P3_10/MCPWM0_BKIN1/OPA2_IP/ADC2_CH8 | bidirectional | PWM0 stop signal 1, OPA2 positive input and ADC2 channel 8. |
| 36 | P3_11/MCPWM0_BKIN2/ADC2_CH7/OPAx_OUT0/REF/EXTI24 | bidirectional | PWM0 stop signal 2, ADC2 channel 7, OPA output port, internal reference voltage (REF) and EXTI24. |
| 37 | P3_13/OPA1_IN/ADC2_CH5/EXTI26 | bidirectional | OPA1 negative input, ADC2 channel 5 and EXTI26. |
| 38 | P3_14/OPA1_IP/ADC2_CH4/EXTI27 | bidirectional | OPA1 positive input, ADC2 channel 4 and EXTI27. |
| 39 | P4_6/MCPWM0_CH1N/EFLS_CLK/ADC1_CH8/OPAx_OUT1/LDO12 | bidirectional | PWM0 channel 1 low side, external flash clock, ADC1 channel 8, OPA output port and 1.2V LDO output (LDO12). |
| 40 | P4_7/ADC1_CH7/DAC1_OUT | bidirectional | ADC1 channel 7 and DAC1 output. |
| 41 | P4_8/CLK/ADC1_CH6/CMP1_IN | bidirectional | Clock gating output, ADC1 channel 6 and comparator 1 negative input. |
| 42 | AVDD | power_in | 3.3V power input. |
| 43 | VSS33 | power_in | Ground (GND) for the 3.3V domain. |
| 44 | P4_13/CMP0_OUT/HALL0_IN2/SPI1_CLK/SCL0/TIM1_Z/TIM2_Z/CAN_TX/EFLS_DAT[0]/ADC0_CH10/CMP0_IP1 | bidirectional | Comparator 0 output, Hall 0 input signal 2, SPI1 clock, I2C0 clock, Timer1 Z-axis signal, Timer2 Z-axis signal, CAN send, external flash data 0, ADC0 channel 10 and comparator 0 positive input 1. |
| 45 | P4_14/CLK/HALL0_IN1/UART2_TXD/SPI1_DO/SDA0/TIM1_CH1/TIM2_CH0/ADC_TRIGGER2/CAN_RX/EFLS_DAT[1]/ADC0_CH9/CMP0_IP2/5VT | bidirectional | Clock output, Hall 0 input signal 1, UART2 send, SPI1 output, I2C0 data, Timer1 channel 1, Timer2 channel 0, ADC trigger signal 2, CAN receive, external flash data 1, ADC0 channel 9 and comparator 0 positive input 2; 5V-tolerant input with 3.3V maximum output. |
| 46 | P4_15/HALL0_IN0/UART2_RXD/SPI1_DI/SCL0/TIM1_CH0/TIM2_CH1/ADC_TRIGGER1/CAN_TMR/EFLS_DAT[2]/ADC0_CH8/CMP0_IP3/5VT | bidirectional | Hall 0 input signal 0, UART2 receive, SPI1 input, I2C0 clock, Timer1 channel 0, Timer2 channel 1, ADC trigger debugging signal 1, CAN external timestamp clock, external flash data 2, ADC0 channel 8 and comparator 0 positive input 3; 5V-tolerant input with 3.3V maximum output. |
| 47 | P5_0/CMP0_OUT/MCPWM0_CH3N/SDA1/TIM3_CH0/ADC_TRIGGER0/EFLS_DAT[3]/ADC0_CH7/CMP0_IN/EXTI32 | bidirectional | Comparator 0 output, PWM0 channel 3 low side, I2C1 data, Timer3 channel 0, ADC trigger debugging signal 0, external flash data 3, ADC0 channel 7, comparator 0 negative input and EXTI32. |
| 48 | P5_1/MCPWM0_CH3P/SPI1_CSN/SCL1/TIM4_CH1/TIM3_CH1/EFLS_CSN/ADC0_CH6/EXTI33 | bidirectional | PWM0 channel 3 high side, SPI1 chip select, I2C1 clock, Timer4 channel 1, Timer3 channel 1, external flash chip select (active low), ADC0 channel 6 and EXTI33. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LINKOSEMI |
| Package | TQFP-48L(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
CAD (KiCad official)
- Symbol:
LKS32MC454CCT8 - Footprint:
Package_QFP:TQFP-48_7x7mm_P0.5mm - 3D model: TQFP-48L(7x7) (KiCad packages3D, STEP)
- 3D model files:
lks32mc454cct8-etched.step/lks32mc454cct8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lks32mc454cct8.step/lks32mc454cct8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LINKOSEMI datasheet (66 pp, sha256
d6cf5b79bab1c87f, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).