component
LM5160QPWPTQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-14-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM5160QPWPTQ1
Texas Instruments · DC-DC Converters · HTSSOP-14-EP
LM5160QPWPTQ1 from Texas Instruments, in a HTSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog ground connection for the internal control circuits. |
| 2 | PGND | power_in | Power ground connection for the internal synchronous rectifier FET. |
| 3 | VIN | power_in | Input supply connection with an operating input range of 4.5 V to 65 V (VIN to AGND absolute maximum is -0.3 V to 70 V). |
| 4 | EN/UVLO | input | Precision enable and input of the UVLO comparator: below 0.35 V the device is shut down, 0.35 V to 1.24 V is standby, and above 1.24 V switching starts once VCC exceeds VCC(UV) = 3.98 V typical; absolute maximum -0.3 V to 70 V. |
| 5 | RON | input | On-time programming pin; a resistor between this pin and VIN sets the switch on-time as a function of input voltage (absolute maximum -0.3 V to 70 V). |
| 6 | SS | input | Soft-start pin; a capacitor from SS to AGND controls output rise time and limits overshoot (absolute maximum -0.3 V to 7 V). |
| 7 | NC | unconnected | No connection. |
| 8 | FPWM | input | Forced PWM logic input: connect to AGND or leave floating for DCM at light loads, or connect to VCC for CCM at all loads and Fly-Buck configuration (absolute maximum -0.3 V to 14 V). |
| 9 | FB | input | Feedback input of the voltage regulation comparator (absolute maximum -0.3 V to 7 V to AGND). |
| 10 | VCC | power_in | Internal high-voltage start-up regulator bypass capacitor pin (absolute maximum -0.3 V to 14 V to AGND). |
| 11 | BST | power_out | Bootstrap capacitor pin; connect a 10-nF or larger ceramic capacitor between BST and SW to bias the high-side gate driver (BST to SW absolute maximum 14 V). |
| 12 | SW | power_out | Switch node: source of the high-side buck FET and drain of the low-side synchronous rectifier; SW to AGND ranges from -1.5 V to 70 V (-3 V for 20 ns transient). |
| 13 | SW | power_out | Switch node: source of the high-side buck FET and drain of the low-side synchronous rectifier; SW to AGND ranges from -1.5 V to 70 V (-3 V for 20 ns transient). |
| 14 | NC | unconnected | No connection. |
| 15 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-14-EP |
| Category | Power Management (PMIC) |
| Pins | 15 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC bias regulator output | VCC | 6.47 | 7.5 | 8.52 | V | VIN = 24 V, ICC = 20 mA | 5 |
| High-side current limit threshold | ILIM (HS) | 2.125 | 2.5 | 2.875 | A | 5 | |
| Current limit forced off-time | TOFF1 | 16 | 29 | 39.8 | µs | VFB = 0 V, VIN = 65 V | 5 |
| Current limit forced off-time | TOFF2 | 2.18 | 3.5 | 5.12 | µs | VFB = 1 V, VIN = 24 V | 5 |
| Sourcing current limit (low-side) | ISOURCE(LS) | 1.9 | 2.5 | 3 | A | 5 | |
| FB regulation level | VREF | 1.975 | 1.995 | 2.015 | V | VIN = 24 V | 5 |
| Error amp source current | IEA(Source) | 7.62 | 10.2 | 12.51 | µA | VFB = 1 V, VSS = 1 V | 6 |
| Error amp sink current | IEA(Sink) | 7.46 | 10 | 12.2 | µA | VFB = 5 V, VSS = 2.25 V | 6 |
| Soft-start charging current | ISS | 7.63 | 10.2 | 12.5 | µA | VSS = 0.5 V | 6 |
| UVLO threshold | VUVLO (TH) | 1.213 | 1.24 | 1.277 | V | VEN/UVLO rising | 6 |
| UVLO hysteresis current | IUVLO(HYS) | 15 | 20 | 25 | µA | VEN/UVLO = 1.4 V | 6 |
| On-time generator TON1 | TON1 | 312 | 428 | 520 | ns | VIN = 24 V, RON = 100 kΩ | 6 |
| On-time generator TON2 | TON2 | 625 | 818 | 1040 | ns | VIN = 24 V, RON = 200 kΩ | 6 |
| On-time generator TON3 | TON3 | 937 | 1247 | 1563 | ns | VIN = 8 V, RON = 100 kΩ | 6 |
| On-time generator TON4 | TON4 | 132 | 176 | 220 | ns | VIN = 65 V, RON = 100 kΩ | 6 |
| Input shutdown current | ISD | 50 | 90.7 | µA | VIN = 24 V, VEN/UVLO = 0 V | 5 | |
| Input operating current | IOP | 2.3 | 2.84 | mA | VIN = 24 V, VFB = 3 V, non-switching | 5 | |
| VIN – VCC dropout voltage | VCC(LDO) | 165 | 260 | mV | VIN = 4.5 V, IVCC = 20 mA | 5 | |
| Bootstrap gate drive UV threshold | BST(UV) | 2.93 | 3.6 | V | VBST – VSW rising | 5 | |
| VCC undervoltage threshold | VCC(UV) | 3.98 | 4.1 | V | VVCC rising | 5 | |
| Shutdown mode threshold | VSD(TH) | 0.28 | 0.35 | V | VEN/UVLO falling | 6 | |
| Input voltage | 4.5 | 65 | V | 4 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| VIN to AGND | -0.3 | 70 | V | 4 | |||
| EN/UVLO to AGND | -0.3 | 70 | V | 4 | |||
| RON to AGND | -0.3 | 70 | V | 4 | |||
| BST to AGND | -0.3 | 84 | V | 4 | |||
| VCC to AGND | -0.3 | 14 | V | 4 | |||
| FPWM to AGND | -0.3 | 14 | V | 4 | |||
| SS to AGND | -0.3 | 7 | V | 4 | |||
| FB to AGND | -0.3 | 7 | V | 4 | |||
| BST to SW | -0.3 | 14 | V | 4 | |||
| BST to VCC | 70 | V | 4 | ||||
| SW to AGND | -1.5 | 70 | V | 4 | |||
| SW to AGND (20-ns transient) | -3 | V | 20-ns transient | 4 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 39.3 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJCbot | 2 | °C/W | 5 | |||
| Junction-to-board thermal characteristic parameter | ψJB | 19.3 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 19.6 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance | RθJCtop | 22.8 | °C/W | 5 | |||
| Junction-to-top thermal characteristic parameter | ψJT | 0.5 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
LM5160QPWPTQ1 - Footprint:
Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-14-EP (KiCad packages3D, STEP)
- 3D model files:
lm5160qpwptq1-etched.step/lm5160qpwptq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5160qpwptq1.step/lm5160qpwptq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
cdd5699ca3b11d90, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).