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74HC595BQ-Q100

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Nexperia Shift Registers, DHVQFN-16-EP(2.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74HC595BQ-Q100

Nexperia · Shift Registers · DHVQFN-16-EP(2.5x3.5)

74HC595BQ-Q100 from Nexperia, in a DHVQFN-16-EP(2.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 tri_state Parallel data output Q1 of the 8-bit storage register; it goes high-impedance when OE is HIGH, and the Qn output current is limited to ±35 mA.
2 Q2 tri_state Parallel data output Q2 of the 8-bit storage register; it goes high-impedance when OE is HIGH, and the Qn output current is limited to ±35 mA.
3 Q3 tri_state Parallel data output Q3 of the 8-bit storage register; it goes high-impedance when OE is HIGH, and the Qn output current is limited to ±35 mA.
4 Q4 tri_state Parallel data output Q4 of the 8-bit storage register; it goes high-impedance when OE is HIGH, and the Qn output current is limited to ±35 mA.
5 Q5 tri_state Parallel data output Q5 of the 8-bit storage register; it goes high-impedance when OE is HIGH, and the Qn output current is limited to ±35 mA.
6 Q6 tri_state Parallel data output Q6 of the 8-bit storage register; it goes high-impedance when OE is HIGH, and the Qn output current is limited to ±35 mA.
7 Q7 tri_state Parallel data output Q7 of the 8-bit storage register; it goes high-impedance when OE is HIGH, and the Qn output current is limited to ±35 mA.
8 GND power_in Ground reference (0 V) for all voltages referenced in the datasheet.
9 Q7S output Serial data output from the 8-stage shift register, used to cascade devices; output current is limited to ±25 mA.
10 MR input Asynchronous master reset, active LOW; a LOW level resets the shift register only and does not affect the storage register.
11 SHCP input Shift register clock input; data is shifted into the shift register on each LOW-to-HIGH transition.
12 STCP input Storage register clock input; shift register contents are transferred to the storage register on a LOW-to-HIGH transition.
13 OE input Output enable, active LOW; a HIGH level forces the Qn outputs into the high-impedance OFF-state without changing the register contents.
14 DS input Serial data input to the 8-stage shift register; inputs include clamp diodes so inputs can exceed VCC through a current-limiting resistor.
15 Q0 tri_state Parallel data output Q0 of the 8-bit storage register; it goes high-impedance when OE is HIGH, and the Qn output current is limited to ±35 mA.
16 VCC power_in Supply voltage; recommended operating range is 2.0 V to 6.0 V for 74HC595-Q100 and absolute maximum is -0.5 V to +7 V.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Nexperia
Package DHVQFN-16-EP(2.5x3.5)
Category Logic
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (recommended operating) VCC 2 5 6 V 6
Input voltage VI 0 V 6
Output voltage VO 0 V 6
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 6
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 6
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 6
Ambient temperature Tamb -40 25 125 °C 6
Supply voltage VCC -0.5 7 V 5
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 5
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 5
Output current, pin Q7S IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V); pin Q7S 5
Output current, pins Qn IO -35 35 mA VO = -0.5 V to (VCC + 0.5 V); pins Qn 5
Supply current ICC 70 mA 5
Ground current IGND -70 mA 5
Storage temperature Tstg -65 150 °C 5
Total power dissipation Ptot 500 mW SOT109-1; SOT403-1; SOT763-1 5
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V 6
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V 6
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V 6
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V 6
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V 6
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V 6
HIGH-level output voltage, all outputs VOH 1.9 2 V VI = VIH or VIL; all outputs; IO = -20 μA; VCC = 2.0 V 6
HIGH-level output voltage, all outputs VOH 4.4 4.5 V VI = VIH or VIL; all outputs; IO = -20 μA; VCC = 4.5 V 6
HIGH-level output voltage, all outputs VOH 5.9 6 V VI = VIH or VIL; all outputs; IO = -20 μA; VCC = 6.0 V 6
HIGH-level output voltage, Q7S output VOH 3.7 4.32 V VI = VIH or VIL; Q7S output; IO = -4 mA; VCC = 4.5 V 6
HIGH-level output voltage, Q7S output VOH 5.2 5.81 V VI = VIH or VIL; Q7S output; IO = -5.2 mA; VCC = 6.0 V 6
HIGH-level output voltage, Qn bus driver outputs VOH 3.7 4.32 V VI = VIH or VIL; Qn bus driver outputs; IO = -6 mA; VCC = 4.5 V 6
HIGH-level output voltage, Qn bus driver outputs VOH 5.2 5.81 V VI = VIH or VIL; Qn bus driver outputs; IO = -7.8 mA; VCC = 6.0 V 6
LOW-level output voltage, all outputs VOL 0 0.1 V VI = VIH or VIL; all outputs; IO = 20 μA; VCC = 2.0 V 7
LOW-level output voltage, Q7S output VOL 0.15 0.4 V VI = VIH or VIL; Q7S output; IO = 4 mA; VCC = 4.5 V 7
LOW-level output voltage, Q7S output VOL 0.16 0.4 V VI = VIH or VIL; Q7S output; IO = 5.2 mA; VCC = 6.0 V 7
LOW-level output voltage, Qn bus driver outputs VOL 0.15 0.4 V VI = VIH or VIL; Qn bus driver outputs; IO = 6 mA; VCC = 4.5 V 7
LOW-level output voltage, Qn bus driver outputs VOL 0.16 0.4 V VI = VIH or VIL; Qn bus driver outputs; IO = 7.8 mA; VCC = 6.0 V 7
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V 7
OFF-state output current IOZ -10 10 μA VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND 7
Supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V 7
Propagation delay SHCP to Q7S tpd 52 240 ns SHCP to Q7S; see Fig. 6; VCC = 2 V 8
Propagation delay SHCP to Q7S tpd 19 48 ns SHCP to Q7S; see Fig. 6; VCC = 4.5 V 8
Propagation delay SHCP to Q7S tpd 15 41 ns SHCP to Q7S; see Fig. 6; VCC = 6 V 8
Propagation delay STCP to Qn tpd 55 265 ns STCP to Qn; see Fig. 7; VCC = 2 V 8
Propagation delay STCP to Qn tpd 20 53 ns STCP to Qn; see Fig. 7; VCC = 4.5 V 8
Propagation delay STCP to Qn tpd 16 45 ns STCP to Qn; see Fig. 7; VCC = 6 V 8
HIGH to LOW propagation delay MR to Q7S tPHL 47 265 ns MR to Q7S; see Fig. 9; VCC = 2 V 8
HIGH to LOW propagation delay MR to Q7S tPHL 17 53 ns MR to Q7S; see Fig. 9; VCC = 4.5 V 8
HIGH to LOW propagation delay MR to Q7S tPHL 14 45 ns MR to Q7S; see Fig. 9; VCC = 6 V 8
Enable time OE to Qn ten 47 225 ns OE to Qn; see Fig. 10; VCC = 2 V 8
Enable time OE to Qn ten 17 45 ns OE to Qn; see Fig. 10; VCC = 4.5 V 8
Enable time OE to Qn ten 14 38 ns OE to Qn; see Fig. 10; VCC = 6 V 8
Disable time OE to Qn tdis 41 225 ns OE to Qn; see Fig. 10; VCC = 2 V 8
Disable time OE to Qn tdis 15 45 ns OE to Qn; see Fig. 10; VCC = 4.5 V 8
Disable time OE to Qn tdis 12 38 ns OE to Qn; see Fig. 10; VCC = 6 V 8
Pulse width SHCP HIGH or LOW tW 110 17 ns SHCP HIGH or LOW; see Fig. 6; VCC = 2 V 9
Pulse width SHCP HIGH or LOW tW 22 6 ns SHCP HIGH or LOW; see Fig. 6; VCC = 4.5 V 9
Pulse width SHCP HIGH or LOW tW 19 5 ns SHCP HIGH or LOW; see Fig. 6; VCC = 6 V 9
Pulse width STCP HIGH or LOW tW 110 11 ns STCP HIGH or LOW; see Fig. 7; VCC = 2 V 9
Pulse width STCP HIGH or LOW tW 22 4 ns STCP HIGH or LOW; see Fig. 7; VCC = 4.5 V 9
Pulse width STCP HIGH or LOW tW 19 3 ns STCP HIGH or LOW; see Fig. 7; VCC = 6 V 9

CAD (KiCad official)

  • Symbol: 74HC595BQ-Q100
  • Footprint: Package_DFN_QFN:DHVQFN-16-1EP_2.5x3.5mm_P0.5mm_EP1x2mm
  • 3D model: DHVQFN-16-EP(2.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 74hc595bq-q100-etched.step / 74hc595bq-q100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc595bq-q100.step / 74hc595bq-q100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (19 pp, sha256 ccdb88dc8760d451, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF