component
74AHC157D
Public Made by Adomby adom
Nexperia Signal Switches, Multiplexers, Decoders, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74AHC157D
Nexperia · Signal Switches, Multiplexers, Decoders · SO-16
74AHC157D from Nexperia, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | input | Common data select input that chooses the nI0 data inputs when LOW and the nI1 data inputs when HIGH. |
| 2 | 1I0 | input | Data input from source 0 for multiplexer channel 1, selected when S is LOW; recommended input voltage range is 0 V to 5.5 V. |
| 3 | 1I1 | input | Data input from source 1 for multiplexer channel 1, selected when S is HIGH; recommended input voltage range is 0 V to 5.5 V. |
| 4 | 1Y | output | Multiplexer output for channel 1, forced LOW when the enable input E is HIGH. |
| 5 | 2I0 | input | Data input from source 0 for multiplexer channel 2, selected when S is LOW; recommended input voltage range is 0 V to 5.5 V. |
| 6 | 2I1 | input | Data input from source 1 for multiplexer channel 2, selected when S is HIGH; recommended input voltage range is 0 V to 5.5 V. |
| 7 | 2Y | output | Multiplexer output for channel 2, forced LOW when the enable input E is HIGH. |
| 8 | GND | power_in | Ground (0 V) reference for all device voltages. |
| 9 | 3Y | output | Multiplexer output for channel 3, forced LOW when the enable input E is HIGH. |
| 10 | 3I1 | input | Data input from source 1 for multiplexer channel 3, selected when S is HIGH; recommended input voltage range is 0 V to 5.5 V. |
| 11 | 3I0 | input | Data input from source 0 for multiplexer channel 3, selected when S is LOW; recommended input voltage range is 0 V to 5.5 V. |
| 12 | 4Y | output | Multiplexer output for channel 4, forced LOW when the enable input E is HIGH. |
| 13 | 4I1 | input | Data input from source 1 for multiplexer channel 4, selected when S is HIGH; recommended input voltage range is 0 V to 5.5 V. |
| 14 | 4I0 | input | Data input from source 0 for multiplexer channel 4, selected when S is LOW; recommended input voltage range is 0 V to 5.5 V. |
| 15 | E | input | Enable input, active LOW; when HIGH all outputs 1Y to 4Y are forced LOW regardless of other inputs. |
| 16 | VCC | power_in | Supply voltage; recommended range is 2.0 V to 5.5 V for 74AHC157 and 4.5 V to 5.5 V for 74AHCT157. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SO-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | 2 | 5 | 5.5 | V | 6 | |
| Input voltage | VI | 0 | 5.5 | V | 6 | ||
| Output voltage | VO | 0 | V | 6 | |||
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 6 | |
| Input transition rise and fall rate | Δt/ΔV | 100 | ns/V | VCC = 3.3 V ± 0.3 V | 6 | ||
| Input transition rise and fall rate | Δt/ΔV | 20 | ns/V | VCC = 5.0 V ± 0.5 V | 6 | ||
| Supply voltage | VCC | -0.5 | 7 | V | 5 | ||
| Input voltage | VI | -0.5 | 7 | V | 5 | ||
| Input clamping current | IIK | -20 | mA | VI < -0.5 V | 5 | ||
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 5 | |
| Output current | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 5 | |
| Supply current | ICC | 75 | mA | 5 | |||
| Ground current | IGND | -75 | mA | 5 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| Total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 5 | ||
| HIGH-level input voltage | VIH | 1.5 | V | VCC = 2.0 V | 6 | ||
| HIGH-level input voltage | VIH | 2.1 | V | VCC = 3.0 V | 6 | ||
| HIGH-level input voltage | VIH | 3.85 | V | VCC = 5.5 V | 6 | ||
| LOW-level input voltage | VIL | 0.5 | V | VCC = 2.0 V | 6 | ||
| LOW-level input voltage | VIL | 0.9 | V | VCC = 3.0 V | 6 | ||
| LOW-level input voltage | VIL | 1.65 | V | VCC = 5.5 V | 6 | ||
| HIGH-level output voltage | VOH | 1.9 | 2 | V | VI = VIH or VIL; IO = -50 μA; VCC = 2.0 V | 6 | |
| HIGH-level output voltage | VOH | 2.9 | 3 | V | VI = VIH or VIL; IO = -50 μA; VCC = 3.0 V | 6 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; IO = -50 μA; VCC = 4.5 V | 6 | |
| HIGH-level output voltage | VOH | 2.4 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 3.0 V | 6 | ||
| HIGH-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; IO = -8.0 mA; VCC = 4.5 V | 6 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 50 μA; VCC = 2.0 V | 6 | |
| LOW-level output voltage | VOL | 0.55 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 3.0 V | 6 | ||
| Input leakage current | II | 2 | μA | VI = 5.5 V or GND; VCC = 0 V to 5.5 V | 6 | ||
| Supply current | ICC | 80 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 6 | ||
| Input capacitance | CI | 3 | 10 | pF | 6 | ||
| Propagation delay nI0, nI1 to nY (CL = 15 pF) | tpd | 1 | 4.4 | 12.5 | ns | VCC = 3.0 V to 3.6 V; CL = 15 pF; see Fig. 5 | 8 |
| Propagation delay nI0, nI1 to nY (CL = 50 pF) | tpd | 1 | 6.3 | 16.5 | ns | VCC = 3.0 V to 3.6 V; CL = 50 pF; see Fig. 5 | 8 |
| Propagation delay nI0, nI1 to nY (CL = 15 pF) | tpd | 1 | 3.2 | 8 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5 | 8 |
| Propagation delay nI0, nI1 to nY (CL = 50 pF) | tpd | 1 | 4.6 | 10.5 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5 | 8 |
| Propagation delay S to nY (CL = 15 pF) | tpd | 1 | 4.8 | 17 | ns | VCC = 3.0 V to 3.6 V; CL = 15 pF; see Fig. 5 | 8 |
| Propagation delay S to nY (CL = 50 pF) | tpd | 1 | 6.8 | 21.5 | ns | VCC = 3.0 V to 3.6 V; CL = 50 pF; see Fig. 5 | 8 |
| Propagation delay S to nY (CL = 15 pF) | tpd | 1 | 3.6 | 11 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 5 | 8 |
| Propagation delay S to nY (CL = 50 pF) | tpd | 1 | 5.2 | 13.5 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 5 | 8 |
| Propagation delay E to nY (CL = 15 pF) | tpd | 1 | 5.9 | 16.5 | ns | VCC = 3.0 V to 3.6 V; CL = 15 pF; see Fig. 6 | 8 |
| Propagation delay E to nY (CL = 50 pF) | tpd | 1 | 8.4 | 21 | ns | VCC = 3.0 V to 3.6 V; CL = 50 pF; see Fig. 6 | 8 |
| Propagation delay E to nY (CL = 15 pF) | tpd | 1 | 4.2 | 10.5 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF; see Fig. 6 | 8 |
| Propagation delay E to nY (CL = 50 pF) | tpd | 1 | 6 | 13 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF; see Fig. 6 | 8 |
CAD (KiCad official)
- Symbol:
74AHC157D - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files:
74ahc157d-etched.step/74ahc157d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74ahc157d.step/74ahc157d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (16 pp, sha256
7a0db500324c30a7, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).