component
CD4518BEE4
Public Made by Adomby adom
Texas Instruments Counters, Dividers, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownCD4518BEE4
Texas Instruments · Counters, Dividers · PDIP-16
CD4518BEE4 from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLOCK A | input | Counter A clock input, which increments the counter on a positive-going edge when ENABLE A is high; clock rise/fall time max 15 µs at 5 V and 5 µs at 10-15 V. |
| 2 | ENABLE A | input | Counter A enable input, which increments the counter on a negative-going edge while CLOCK A is low, and is held high for single-unit operation. |
| 3 | Q1A | output | Counter A stage 1 (first-stage) output. |
| 4 | Q2A | output | Counter A stage 2 output. |
| 5 | Q3A | output | Counter A stage 3 output. |
| 6 | Q4A | output | Counter A stage 4 output, which can be connected to the ENABLE input of the next counter for ripple cascading while its CLOCK is held low. |
| 7 | RESET A | input | Counter A reset input; a high level clears Q1 through Q4 of counter A to 0, with minimum reset pulse width 250 ns at 5 V. |
| 8 | VSS | power_in | Ground / negative supply terminal, the reference for all voltage ratings. |
| 9 | CLOCK B | input | Counter B clock input, which increments the counter on a positive-going edge when ENABLE B is high. |
| 10 | ENABLE B | input | Counter B enable input, which increments the counter on a negative-going edge while CLOCK B is low, and is held high for single-unit operation. |
| 11 | Q1B | output | Counter B stage 1 (first-stage) output. |
| 12 | Q2B | output | Counter B stage 2 output. |
| 13 | Q3B | output | Counter B stage 3 output. |
| 14 | Q4B | output | Counter B stage 4 output, which can be used for ripple cascading to another counter's ENABLE input. |
| 15 | RESET B | input | Counter B reset input; a high level clears Q1 through Q4 of counter B to 0. |
| 16 | VDD | power_in | Positive supply terminal, recommended 3 V to 18 V with absolute maximum of -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4518BEE4 - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: PDIP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4518bee4-etched.step/cd4518bee4-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4518bee4.step/cd4518bee4.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
c28162391ada6d6a, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).