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MSP430F5501IRGZT

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

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MSP430F5501IRGZT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)

MSP430F5501IRGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P6.0/CB0 bidirectional General-purpose digital I/O; also Comparator_B input CB0. No ADC input on F5501 (A0 not available).
2 P6.1/CB1 bidirectional General-purpose digital I/O; also Comparator_B input CB1. No ADC input on F5501.
3 P6.2/CB2 bidirectional General-purpose digital I/O; also Comparator_B input CB2. No ADC input on F5501.
4 P6.3/CB3 bidirectional General-purpose digital I/O; also Comparator_B input CB3. No ADC input on F5501.
5 P5.0 bidirectional General-purpose digital I/O. ADC channel A8 and external reference VeREF+ not available on the F5501 variant.
6 P5.1 bidirectional General-purpose digital I/O. ADC channel A9 and external reference VeREF- not available on the F5501 variant.
7 AVCC1 power_in Analog power supply. Recommended tied to DVCC1 (0.3 V max difference during power-up/operation). Supply range 1.8 V to 3.6 V.
8 P5.4/XIN bidirectional General-purpose digital I/O; input terminal for the low-frequency crystal oscillator XT1 (typically 32.768 kHz watch crystal).
9 P5.5/XOUT bidirectional General-purpose digital I/O; output terminal for the low-frequency crystal oscillator XT1.
10 AVSS1 power_in Analog ground supply.
11 DVCC1 power_in Digital power supply. 1.8 V to 3.6 V. Recommended to be tied to AVCC1.
12 DVSS1 power_in Digital ground supply.
13 VCORE passive Regulated core supply output from internal LDO. Internal use only, no external DC loading. Connect a 470 nF capacitor (CVCORE) to VSS; ratio CDVCC/CVCORE ≥ 10.
14 P1.0/TA0CLK/ACLK bidirectional General-purpose digital I/O with port interrupt; TA0 external clock TA0CLK input; ACLK output (divided by 1/2/4/8/16/32).
15 P1.1/TA0.0 bidirectional General-purpose digital I/O with port interrupt; TA0 CCR0 capture (CCI0A) input / compare (Out0) output; BSL transmit output.
16 P1.2/TA0.1 bidirectional General-purpose digital I/O with port interrupt; TA0 CCR1 capture (CCI1A) / compare (Out1); BSL receive input.
17 P1.3/TA0.2 bidirectional General-purpose digital I/O with port interrupt; TA0 CCR2 capture (CCI2A) input / compare (Out2) output.
18 P1.4/TA0.3 bidirectional General-purpose digital I/O with port interrupt; TA0 CCR3 capture (CCI3A) input / compare (Out3) output.
19 P1.5/TA0.4 bidirectional General-purpose digital I/O with port interrupt; TA0 CCR4 capture (CCI4A) input / compare (Out4) output.
20 P1.6/TA1CLK bidirectional General-purpose digital I/O with port interrupt; TA1 external clock TA1CLK input. (CBOUT function is present on other packages but not on this RGZ pin per Figure 4-5.)
21 P1.7/TA1.0 bidirectional General-purpose digital I/O with port interrupt; TA1 CCR0 capture (CCI0A) / compare (Out0).
22 P2.0/TA1.1 bidirectional General-purpose digital I/O with port interrupt; TA1 CCR1 capture (CCI1A) / compare (Out1).
23 PJ.0/TDO bidirectional General-purpose digital I/O (port PJ); JTAG test data output (TDO).
24 PJ.1/TDI/TCLK bidirectional General-purpose digital I/O (port PJ); JTAG test data input (TDI) and test clock (TCLK).
25 PJ.2/TMS bidirectional General-purpose digital I/O (port PJ); JTAG test mode select (TMS).
26 PJ.3/TCK bidirectional General-purpose digital I/O (port PJ); JTAG test clock (TCK).
27 DVSS2 power_in Digital ground supply (second DVSS pin).
28 DVCC2 power_in Digital power supply (second DVCC pin), 1.8 V to 3.6 V. Tie to DVCC1/AVCC1.
29 P4.0/PM_UCB1STE/PM_UCA1CLK bidirectional General-purpose digital I/O with reconfigurable port-map secondary function. Default map: USCI_B1 SPI slave-transmit-enable (STE); USCI_A1 SPI clock (in slave / out master).
30 P4.1/PM_UCB1SIMO/PM_UCB1SDA bidirectional General-purpose digital I/O with reconfigurable port-map secondary function. Default map: USCI_B1 SPI SIMO (slave-in/master-out); USCI_B1 I2C data (SDA).
31 P4.2/PM_UCB1SOMI/PM_UCB1SCL bidirectional General-purpose digital I/O with reconfigurable port-map secondary function. Default map: USCI_B1 SPI SOMI (slave-out/master-in); USCI_B1 I2C clock (SCL).
32 P4.3/PM_UCB1CLK/PM_UCA1STE bidirectional General-purpose digital I/O with reconfigurable port-map secondary function. Default map: USCI_B1 SPI clock (in slave / out master); USCI_A1 SPI slave-transmit-enable.
33 P4.4/PM_UCA1TXD/PM_UCA1SIMO bidirectional General-purpose digital I/O with reconfigurable port-map secondary function. Default map: USCI_A1 UART TXD; USCI_A1 SPI SIMO.
34 P4.5/PM_UCA1RXD/PM_UCA1SOMI bidirectional General-purpose digital I/O with reconfigurable port-map secondary function. Default map: USCI_A1 UART RXD; USCI_A1 SPI SOMI.
35 P4.6/PM_NONE bidirectional General-purpose digital I/O with reconfigurable port-map secondary function. Default map: no secondary function (available for user-selected port-map assignment).
36 P4.7/PM_NONE bidirectional General-purpose digital I/O with reconfigurable port-map secondary function. Default map: no secondary function.
37 VSSU power_in USB PHY ground supply.
38 PU.0/DP bidirectional USB full-speed D+ data terminal (also general-purpose digital I/O when controlled by USB control register).
39 PUR bidirectional USB pullup resistor pin (open-drain). Voltage level here at reset selects USB BSL entry; recommended 1 MΩ to ground.
40 PU.1/DM bidirectional USB full-speed D- data terminal (also general-purpose digital I/O when controlled by USB control register).
41 VBUS power_in USB LDO input; connect to USB VBUS (5 V from USB host/hub) when USB is used.
42 VUSB power_out USB LDO output (3.3 V nominal); requires external bypass capacitor per datasheet.
43 V18 passive USB regulated 1.8 V power (internal use only, no external DC loading). Bypass capacitor only.
44 AVSS2 power_in Analog ground supply (second AVSS pin).
45 P5.2/XT2IN bidirectional General-purpose digital I/O; input terminal for the high-frequency crystal oscillator XT2 (up to 32 MHz).
46 P5.3/XT2OUT bidirectional General-purpose digital I/O; output terminal for the high-frequency crystal oscillator XT2.
47 TEST/SBWTCK input Test mode pin - selects digital I/O function on JTAG pins; also Spy-Bi-Wire (SBW) input clock.
48 RST/NMI/SBWTDIO bidirectional Active-low reset input (internal pullup enabled when configured as reset); nonmaskable interrupt input; Spy-Bi-Wire data I/O.
49 PAD power_in Exposed QFN thermal pad on the underside of the package. TI recommends connecting to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Embedded Processors & Controllers
Pins 49

Ordering variants

Same part, different packaging or reel option.

  • MSP430F5501IRGZR
  • MSP430F5501IRGZT

CAD (KiCad official)

  • Symbol: MSP430F5501IRGZT
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 39e075da0f1e3944, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF