component
N32L406CBL7
Public Made by Adomby adom
Nations Technologies Inc Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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README
markdownN32L406CBL7
Nations Technologies Inc · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
N32L406CBL7 from Nations Technologies Inc, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VLCD | power_in | Segment LCD supply pin; it can be driven from an external supply (connect VLCD to VDD) or used with the internal boost converter, which requires a 1 µF capacitor on VLCD. |
| 2 | PC13-TAMPER-RTC | bidirectional | Fail-safe 3.3V standard I/O that can only sink limited current (3 mA); as an output it allows only one such pin at a time, 2 MHz mode, 30 pF maximum load and no current-source use. Alternates include TIM1_CH1N, LCD_SEG35, TAMP1-RTC, RTC_OUT and WKUP2. |
| 3 | PC14-OSC32_IN | bidirectional | Fail-safe 3.3V standard I/O with the same 3 mA and output restrictions as PC13; it serves as the LSE 32.768 kHz oscillator input (OSC32_IN). |
| 4 | PC15-OSC32_OUT | bidirectional | Fail-safe 3.3V standard I/O with the same 3 mA and output restrictions as PC13; it serves as the LSE 32.768 kHz oscillator output (OSC32_OUT). |
| 5 | PD14-OSC_IN | bidirectional | 3.3V standard I/O, not fail-safe; it serves as the HSE 4-32 MHz oscillator input (OSC_IN) and also carries USART2_TX, I2C2_SDA and TIM1_CH3N. |
| 6 | PD15-OSC_OUT | bidirectional | 3.3V standard I/O, not fail-safe; it serves as the HSE oscillator output (OSC_OUT) and also carries USART2_RX and I2C2_SCL. |
| 7 | NRST | input | Reset input with a non-disconnectable internal pull-up of 40-60 kΩ at 3.3 V; input filter pulses under 100 ns are ignored and pulses over 300 ns are not filtered. |
| 8 | VSSA | power_in | Ground for the analog section (ADC, DAC, OPAMP, COMP, TSC), which must be connected to VSS; also serves as the VREF- reference ground. |
| 9 | VDDA | power_in | Analog supply for ADC, DAC, OPAMP, COMP and TSC, 1.8-3.6 V, which must be the same supply as VDD (at most 300 mV difference during power-up and operation); also serves as VREF+. |
| 10 | PA0 | bidirectional | Fail-safe 3.3V standard I/O with ADC_IN1, COMP1_OUT, WKUP1 and TIM2_CH1/TIM5_CH1 alternate functions. |
| 11 | PA1 | bidirectional | Fail-safe 3.3V standard I/O with ADC1_IN2, LCD_SEG0, LPUART_TX and TIM5_CH2 alternate functions. |
| 12 | PA2 | bidirectional | Fail-safe 3.3V standard I/O with ADC_IN3, COMP2_OUT, LCD_SEG1, TSC_CH1 and USART2_TX alternate functions. |
| 13 | PA3 | bidirectional | Fail-safe 3.3V standard I/O with ADC_IN4, LCD_SEG2, USART2_RX and TSC_CH4 alternate functions. |
| 14 | PA4 | bidirectional | 3.3V standard I/O, not fail-safe; carries ADC_IN5, DAC_OUT, USART2_CK, SPI1_NSS and I2S1_WS alternate functions. |
| 15 | PA5 | bidirectional | Fail-safe 3.3V standard I/O with ADC_IN6, SPI1_SCK, I2S1_CK, USART1_RX and TSC_CH6 alternate functions. |
| 16 | PA6 | bidirectional | Fail-safe 3.3V standard I/O with ADC_IN7, SPI1_MISO, TIM3_CH1, TIM8_BKIN and LCD_SEG3 alternate functions. |
| 17 | PA7 | bidirectional | Fail-safe 3.3V standard I/O with ADC_IN8, SPI1_MOSI, TIM3_CH2, TIM1_CH1N and LCD_SEG4 alternate functions. |
| 18 | PB0 | bidirectional | Fail-safe 3.3V standard I/O with ADC_IN9, TIM3_CH3, TIM1_CH2N, LCD_SEG5 and TSC_CH7 alternate functions. |
| 19 | PB1 | bidirectional | Fail-safe 3.3V standard I/O with ADC_IN10, TIM3_CH4, LCD_SEG6, UART4_RX and TSC_CH8 alternate functions. |
| 20 | PB2 | bidirectional | Fail-safe 3.3V standard I/O with LPTIM_OUT, TIM9_ETR and TSC_CH9 alternate functions. |
| 21 | PB10 | bidirectional | Fail-safe 3.3V standard I/O with USART3_TX, LPUART_TX, I2C2_SCL, LCD_SEG10 and TSC_CH19 alternate functions. |
| 22 | PB11 | bidirectional | Fail-safe 3.3V standard I/O with USART3_RX, LPUART_RX, I2C2_SDA, LCD_SEG11 and TSC_CH10 alternate functions. |
| 23 | VSS | power_in | Digital ground; must be connected to the external ground system. |
| 24 | VDD | power_in | Digital supply for I/O pins and the internal regulator, 1.8-3.6 V. |
| 25 | PB12 | bidirectional | Fail-safe 3.3V standard I/O with SPI2_NSS, I2S2_WS, USART3_CK, TIM1_BKIN, LCD_SEG12 and TSC_CH11 alternate functions. |
| 26 | PB13 | bidirectional | Fail-safe 3.3V standard I/O with SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, LCD_SEG13 and TSC_CH16 alternate functions. |
| 27 | PB14 | bidirectional | Fail-safe 3.3V standard I/O with SPI2_MISO, I2S2_MCK, TIM1_CH2N, USART3_RTS, I2C2_SDA and OPAMP2_VINP alternate functions. |
| 28 | PB15 | bidirectional | Fail-safe 3.3V standard I/O with SPI2_MOSI, I2S2_SD, TIM1_CH3N, UART4_RX, LCD_SEG15 and TSC_CH15 alternate functions. |
| 29 | PA8 | bidirectional | Fail-safe 3.3V standard I/O with MCO, USART1_CK, TIM1_CH1, LCD_COM0, I2C2_SMBA and WKUP0 alternate functions. |
| 30 | PA9 | bidirectional | Fail-safe 3.3V standard I/O with USART1_TX, I2C2_SCL, TIM1_CH2 and LCD_COM1 alternate functions. |
| 31 | PA10 | bidirectional | Fail-safe 3.3V standard I/O with USART1_RX, I2C2_SDA, SPI1_SCK, TIM1_CH3 and LCD_COM2 alternate functions. |
| 32 | PA11 | bidirectional | 3.3V standard I/O, not fail-safe; it serves as USB_DM (USB full-speed D-) on N32L403/N32L406 and also carries USART1_CTS, CAN_RX, TIM1_CH4 and COMP1_OUT. |
| 33 | PA12 | bidirectional | 3.3V standard I/O, not fail-safe; it serves as USB_DP (USB full-speed D+) on N32L403/N32L406 and also carries USART1_RTS, CAN_TX, TIM1_ETR and COMP2_OUT. |
| 34 | PA13 | bidirectional | Fail-safe 3.3V standard I/O that is also the SWDIO-JTMS serial-wire debug data pin. |
| 35 | VSS | power_in | Digital ground; must be connected to the external ground system. |
| 36 | VDD | power_in | Digital supply for I/O pins and the internal regulator, 1.8-3.6 V. |
| 37 | PA14 | bidirectional | Fail-safe 3.3V standard I/O that is also the SWCLK-JTCK debug clock pin, with USART2_CK, I2C1_SDA and COMP2_OUT alternates. |
| 38 | PA15 | bidirectional | Fail-safe 3.3V standard I/O that is also the JTDI debug input, with USART2_CTS, SPI2_NSS, I2S2_WS, TIM2_CH1 and LCD_SEG17/LCD_COM3 alternates. |
| 39 | PB3 | bidirectional | Fail-safe 3.3V standard I/O that is also the JTDO-TRACESWO trace output, with SPI1_SCK, I2S1_CK, USART2_RTS, TIM2_CH2 and LCD_SEG7 alternates. |
| 40 | PB4 | bidirectional | Fail-safe 3.3V standard I/O with USART2_TX, SPI1_MISO, I2S1_MCK, TIM3_CH1, LCD_SEG8 and UART5_TX alternate functions. |
| 41 | PB5 | bidirectional | Fail-safe 3.3V standard I/O with USART2_RX, I2C1_SMBA, SPI1_MOSI, TIM3_CH2, LCD_SEG9, UART5_RX and LPTIM_IN1 alternate functions. |
| 42 | PB6 | bidirectional | Fail-safe 3.3V standard I/O with USART1_TX, LPUART_TX, I2C1_SCL, SPI1_NSS, TIM4_CH1 and LPTIM_ETR alternate functions. |
| 43 | PB7 | bidirectional | Fail-safe 3.3V standard I/O with USART1_RX, LPUART_RX, I2C1_SDA, TIM4_CH2, TSC_OUT, LPTIM_IN2 and PVD_IN alternate functions. |
| 44 | BOOT0/PD0 | bidirectional | Fail-safe 3.3V standard I/O that is the BOOT0 boot-mode select input, which has an input pull-down; it also carries TRACECK and LCD_SEG32. |
| 45 | PB8 | bidirectional | Fail-safe 3.3V standard I/O with I2C1_SCL, CAN_RX, TIM4_CH3, LCD_SEG16, USART1_TX, UART5_TX and COMP1_OUT alternate functions. |
| 46 | PB9 | bidirectional | Fail-safe 3.3V standard I/O with I2C1_SDA, CAN_TX, TIM4_CH4, LCD_COM3, UART5_RX and COMP2_OUT alternate functions. |
| 47 | VSS | power_in | Digital ground; must be connected to the external ground system. |
| 48 | VDD | power_in | Digital supply for I/O pins and the internal regulator, 1.8-3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nations Technologies Inc |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 输入低电平电压 (VIL), VDD=3.3V | VIL | 0.8 | V | VDD=3.3V; min printed as VSS (not numeric) | 65 | ||
| 输入低电平电压 (VIL), VDD=2.5V | VIL | 0.7 | V | VDD=2.5V; min printed as VSS (not numeric) | 65 | ||
| 输入高电平电压 (VIH), VDD=3.3V | VIH | 2 | V | VDD=3.3V; max printed as VDD (not numeric) | 65 | ||
| 输入高电平电压 (VIH), VDD=2.5V | VIH | 1.7 | V | VDD=2.5V; max printed as VDD (not numeric) | 65 | ||
| 施密特触发器电压迟滞 (Vhys), VDD=3.3V/2.5V | Vhys | 200 | mV | VDD=3.3V/2.5V | 65 | ||
| 输入漏电流 (Ilkg) | Ilkg | -1 | 1 | μA | VDD=Maximum, VPAD=0 or VPAD=VDD | 65 | |
| 弱上拉等效电阻 (RPU), I/O | RPU | 90 | 170 | kΩ | VDD=3.3V, VIN=VSS | 65 | |
| 弱下拉等效电阻 (RPD), I/O | RPD | 90 | 170 | kΩ | VDD=3.3V, VIN=VDD | 65 | |
| I/O引脚的电容 (CIO) | CIO | 0.1 | pF | 65 | |||
| 输出低电平 (VOL), VDD=3.3V | VOL | 0.4 | V | VDD=3.3V, IOL=2,4,8,12mA; min printed as VSS | 65 | ||
| 输出低电平 (VOL), VDD=2.5V | VOL | 0.4 | V | VDD=2.5V, IOL=2,4,8,12mA; min printed as VSS | 65 | ||
| 输出高电平 (VOH), VDD=3.3V | VOH | 2.4 | V | VDD=3.3V, IOH=-2,-4,-8,-12mA; max printed as VDD | 65 | ||
| 输出高电平 (VOH), VDD=2.5V | VOH | 2 | V | VDD=2.5V, IOH=-2,-4,-8,-12mA; max printed as VDD | 65 | ||
| 最大频率 (fmax(IO)out), PMODE 00 (2mA) | fmax(IO)out | 75 | MHz | PMODEy=00 (2mA), CL=5pF, VDD=3.3V | 66 | ||
| 最大频率 (fmax(IO)out), PMODE 00 (2mA) | fmax(IO)out | 50 | MHz | PMODEy=00 (2mA), CL=5pF, VDD=2.5V | 66 | ||
| 最大频率 (fmax(IO)out), PMODE 00 (2mA) | fmax(IO)out | 30 | MHz | PMODEy=00 (2mA), CL=5pF, VDD=1.8V | 66 | ||
| 输出延时 (t(IO)out), PMODE 00 (2mA) | t(IO)out | 3.66 | ns | PMODEy=00 (2mA), CL=5pF, VDD=3.3V (a to pad) | 66 | ||
| 输出延时 (t(IO)out), PMODE 00 (2mA) | t(IO)out | 4.72 | ns | PMODEy=00 (2mA), CL=5pF, VDD=2.5V (a to pad) | 66 | ||
| 输出延时 (t(IO)out), PMODE 00 (2mA) | t(IO)out | 7.12 | ns | PMODEy=00 (2mA), CL=5pF, VDD=1.8V (a to pad) | 66 | ||
| 最大频率 (fmax(IO)out), PMODE 01 (4mA) | fmax(IO)out | 90 | MHz | PMODEy=01 (4mA), CL=10pF, VDD=3.3V | 66 | ||
| 最大频率 (fmax(IO)out), PMODE 01 (4mA) | fmax(IO)out | 60 | MHz | PMODEy=01 (4mA), CL=10pF, VDD=2.5V | 66 | ||
| 最大频率 (fmax(IO)out), PMODE 01 (4mA) | fmax(IO)out | 40 | MHz | PMODEy=01 (4mA), CL=10pF, VDD=1.8V | 66 | ||
| 输出延时 (t(IO)out), PMODE 01 (4mA) | t(IO)out | 3.5 | ns | PMODEy=01 (4mA), CL=10pF, VDD=3.3V (a to pad) | 66 | ||
| 输出延时 (t(IO)out), PMODE 01 (4mA) | t(IO)out | 4.5 | ns | PMODEy=01 (4mA), CL=10pF, VDD=2.5V (a to pad) | 66 | ||
| 输出延时 (t(IO)out), PMODE 01 (4mA) | t(IO)out | 6.74 | ns | PMODEy=01 (4mA), CL=10pF, VDD=1.8V (a to pad) | 66 | ||
| 最大频率 (fmax(IO)out), PMODE 10 (8mA) | fmax(IO)out | 75 | MHz | PMODEy=10 (8mA), CL=20pF, VDD=3.3V | 66 | ||
| 最大频率 (fmax(IO)out), PMODE 10 (8mA) | fmax(IO)out | 50 | MHz | PMODEy=10 (8mA), CL=20pF, VDD=2.5V | 66 | ||
| 最大频率 (fmax(IO)out), PMODE 10 (8mA) | fmax(IO)out | 30 | MHz | PMODEy=10 (8mA), CL=20pF, VDD=1.8V | 66 | ||
| 输出延时 (t(IO)out), PMODE 10 (8mA) | t(IO)out | 3.42 | ns | PMODEy=10 (8mA), CL=20pF, VDD=3.3V (a to pad) | 66 | ||
| 输出延时 (t(IO)out), PMODE 10 (8mA) | t(IO)out | 4.73 | ns | PMODEy=10 (8mA), CL=20pF, VDD=2.5V (a to pad) | 66 | ||
| 输出延时 (t(IO)out), PMODE 10 (8mA) | t(IO)out | 6.53 | ns | PMODEy=10 (8mA), CL=20pF, VDD=1.8V (a to pad) | 66 | ||
| 最大频率 (fmax(IO)out), PMODE 11 (12mA) | fmax(IO)out | 75 | MHz | PMODEy=11 (12mA), CL=30pF, VDD=3.3V | 66 | ||
| 最大频率 (fmax(IO)out), PMODE 11 (12mA) | fmax(IO)out | 50 | MHz | PMODEy=11 (12mA), CL=30pF, VDD=2.5V | 66 | ||
| 最大频率 (fmax(IO)out), PMODE 11 (12mA) | fmax(IO)out | 30 | MHz | PMODEy=11 (12mA), CL=30pF, VDD=1.8V | 66 | ||
| 输出延时 (t(IO)out), PMODE 11 (12mA) | t(IO)out | 3.34 | ns | PMODEy=11 (12mA), CL=30pF, VDD=3.3V (a to pad) | 66 | ||
| 输出延时 (t(IO)out), PMODE 11 (12mA) | t(IO)out | 4.26 | ns | PMODEy=11 (12mA), CL=3pF (as printed), VDD=2.5V (a to pad) | 66 | ||
| 输出延时 (t(IO)out), PMODE 11 (12mA) | t(IO)out | 6.34 | ns | PMODEy=11 (12mA), CL=3pF (as printed), VDD=1.8V (a to pad) | 66 | ||
| 输入延时 (t(IO)in), pad to y | t(IO)in | 1.2 | ns | CL=50fF, VDD=2.97V, VDDD=0.81V; input characteristics at 1.8V and 2.5V are derated | 66 | ||
| NRST输入低电平电压 (VIL(NRST)) | VIL(NRST) | 0.8 | V | VDD=3.3v; min printed as Vss | 67 | ||
| NRST输入高电平电压 (VIH(NRST)) | VIH(NRST) | 2 | V | VDD=3.3v; max printed as VDD (not numeric) | 67 | ||
| NRST施密特触发器电压迟滞 (Vhys(NRST)) | Vhys(NRST) | 200 | mV | 67 | |||
| NRST弱上拉等效电阻 (RPU) | RPU | 40 | 50 | 60 | kΩ | VDD=3.3v | 67 |
| NRST输入滤波脉冲 (VF(NRST)) | VF(NRST) | 100 | ns | 67 | |||
| 定时器分辨时间 (tres(TIM)) | tres(TIM) | 1 | tTIMxCLK | 68 | |||
| 定时器分辨时间 (tres(TIM)) | tres(TIM) | 15.625 | ns | fTIMxCLK=64MHz | 68 | ||
| CH1至CH2的定时器外部时钟频率 (fEXT) | fEXT | 0 | 64 | MHz | fTIMxCLK=64MHz | 68 | |
| 定时器分辨率 (ResTIM) | ResTIM | 16 | 位 | 68 | |||
| 供电电压 (VDDA) | VDDA | 1.8 | 3.6 | V | 使用外部参考电压 (using external reference voltage) | 75 | |
| 正参考电压 (VREF+) | VREF+ | 1.8 | V | max printed as VDDA (not numeric) | 75 | ||
| ADC时钟频率 (fADC) | fADC | 64 | MHz | 75 | |||
| 采样速率 (fs) | fs | 4.57 | MHz | 75 | |||
| 综合误差 (ET) | ET | -5 | 5 | LSB | fHCLK=64MHz, fADC=64MHz, sample rate=1.75Msps, VDDA=3.3V, TA=25°C, VREF+=VDDA, after calibration | 75 | |
| LCD外部电压 (VLCD) | VLCD | 3.6 | V | 71 | |||
| VSENSE线性度 (TL) | TL | -4 | 4 | ºC | 72 |
CAD (KiCad official)
- Symbol:
N32L406CBL7 - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
n32l406cbl7-etched.step/n32l406cbl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);n32l406cbl7.step/n32l406cbl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nations Technologies Inc datasheet (90 pp, sha256
5f82e78c0fff8967, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).