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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

LMH0397RTVR

Texas Instruments · Video Interface ICs · WQFN-32-EP(5x5)

LMH0397RTVR from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SDI_IO+	bidirectional	Single-ended complementary 75-Ω SDI port with on-chip termination and return-loss network, used as the cable equalizer input in EQ mode or cable driver output in CD mode, AC-coupled with 4.7 µF to the BNC.
2	SDI_IO-	bidirectional	Complementary half of the SDI_IO± port, AC-coupled with 4.7 µF and terminated with an external 75-Ω resistor to GND.
3	VSS	power_in	Ground reference.
4	OUT0_SEL	input	Enables the 100-Ω host-side output driver at OUT0±; internally pulled high by default (OUT0 disabled), although OUT0 is enabled by default in EQ mode regardless of this pin.
5	EQ/CD_SEL	input	Selects the signal direction of the bidirectional I/O as adaptive equalizer (EQ mode) or cable driver (CD mode); internally pulled low by default (EQ mode).
6	VSS	power_in	Ground reference.
7	SDI_OUT-	output	Complementary half of the SDI_OUT± 75-Ω output with on-chip termination, used as loop-through output in EQ mode or second fan-out cable driver in CD mode, AC-coupled with 4.7 µF and terminated with an external 75-Ω resistor to GND.
8	SDI_OUT+	output	Single-ended complementary 75-Ω output with on-chip termination and return-loss network, used as loop-through output in EQ mode or second fan-out cable driver in CD mode, AC-coupled with 4.7 µF to the BNC.
9	HOST_EQ0	input	4-level pin that selects the OUT0± driver VOD and de-emphasis in EQ mode and the IN0± equalizer setting in CD mode.
10	RSV1	unconnected	Reserved pin; do not connect.
11	SS_N_ADDR0	input	In SPI mode this is the active-low slave select (2.5-V LVCMOS, internally pulled high); in SMBus mode it is the 4-level address strap ADDR0 read at power-up.
12	MODE_SEL	input	4-level pin that selects SPI (float) or SMBus (1 kΩ to VSS) control; levels H and R are reserved for factory testing and must not be used.
13	MOSI_SDA	bidirectional	In SPI mode this is the 2.5-V LVCMOS MOSI data input; in SMBus mode it is the 3.3-V tolerant open-drain SDA data line that requires an external pullup to the SMBus termination voltage.
14	SDI_OUT_SEL	input	Enables the 75-Ω output driver at SDI_OUT±; internally pulled high by default (SDI_OUT disabled).
15	RSV2	unconnected	Reserved pin; do not connect.
16	RSV3	unconnected	Reserved pin; do not connect.
17	OUT_CTRL	input	4-level pin that selects the signal routed to the output, enabling or bypassing the reclocker and the cable equalizer.
18	IN0-	input	Differential host video processor input with on-chip 100-Ω differential termination, requiring external 4.7-µF AC-coupling capacitors for SMPTE applications.
19	IN0+	input	Differential host video processor input with on-chip 100-Ω differential termination, requiring external 4.7-µF AC-coupling capacitors for SMPTE applications.
20	VSS	power_in	Ground reference.
21	VDD_CDR	power_in	Powers the reclocker circuitry and is connected to the same 2.5-V ±5% supply as VIN.
22	OUT0-	output	Differential host-side output with on-chip 100-Ω differential termination, requiring external 4.7-µF AC-coupling capacitors for SMPTE applications.
23	OUT0+	output	Differential host-side output with on-chip 100-Ω differential termination, requiring external 4.7-µF AC-coupling capacitors for SMPTE applications.
24	SDI_VOD	input	4-level pin that selects one of four output amplitudes for the cable drivers at SDI_IO± and SDI_OUT±.
25	RSV4	unconnected	Reserved pin; do not connect.
26	RSV5	unconnected	Reserved pin; do not connect.
27	LOCK_N	output	3.3-V tolerant, active-low open-drain reclocker lock indicator (also configurable as CD_N or INT_N) that requires an external resistor to a logic supply.
28	MISO_ADDR1	output	In SPI mode this is the 2.5-V LVCMOS MISO serial data output; in SMBus mode it is the 4-level address strap ADDR1 read at power-up.
29	SCK_SCL	bidirectional	In SPI mode this is the 2.5-V LVCMOS serial clock input (external pullup recommended); in SMBus mode it is the 3.3-V tolerant open-drain SCL clock that requires an external pullup to the SMBus termination voltage.
30	VIN	power_in	Connected to an external 2.5-V ±5% power supply (2.375 V to 2.625 V).
31	VDD_LDO	power_out	Output of the internal 1.8-V LDO regulator that powers internal circuitry only and requires external 1-µF and 0.1-µF bypass capacitors to VSS.
32	ENABLE	input	Logic high enables normal operation and logic low places the device in power-down mode; internally pulled high by default.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-32-EP(5x5)
Category	Interface
Pins	33

CAD (KiCad official)

Symbol: LMH0397RTVR
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: lmh0397rtvr-etched.step / lmh0397rtvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmh0397rtvr.step / lmh0397rtvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (48 pp, sha256 6e0470df8d07a8c0, retrieved 2026-10-11, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF