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Contents

README

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SN74LV240ADWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-20

SN74LV240ADWR from Texas Instruments, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable 1 (active low): when low, the 1A inputs pass inverted data to the 1Y outputs; when high, outputs 1Y1-1Y4 are high-impedance.
2 1A1 input Data input 1A1 to the first buffer of the 1Y group; the output is the inverse of this input when 1OE is low.
3 2Y4 output Inverted, 3-state output of the 2A4 buffer in the second 4-bit group; high-impedance when 2OE is high.
4 1A2 input Data input 1A2 to the 1Y group; the output is the inverse of this input when 1OE is low.
5 2Y3 output Inverted, 3-state output of the 2A3 buffer in the second 4-bit group; high-impedance when 2OE is high.
6 1A3 input Data input 1A3 to the 1Y group; the output is the inverse of this input when 1OE is low.
7 2Y2 output Inverted, 3-state output of the 2A2 buffer in the second 4-bit group; high-impedance when 2OE is high.
8 1A4 input Data input 1A4 to the 1Y group; the output is the inverse of this input when 1OE is low.
9 2Y1 output Inverted, 3-state output of the 2A1 buffer in the second 4-bit group; high-impedance when 2OE is high.
10 GND power_in Ground pin, the device reference potential.
11 2A1 input Data input 2A1 to the 2Y group; the output is the inverse of this input when 2OE is low.
12 1Y4 output Inverted, 3-state output of the 1A4 buffer in the first 4-bit group; high-impedance when 1OE is high.
13 2A2 input Data input 2A2 to the 2Y group; the output is the inverse of this input when 2OE is low.
14 1Y3 output Inverted, 3-state output of the 1A3 buffer in the first 4-bit group; high-impedance when 1OE is high.
15 2A3 input Data input 2A3 to the 2Y group; the output is the inverse of this input when 2OE is low.
16 1Y2 output Inverted, 3-state output of the 1A2 buffer in the first 4-bit group; high-impedance when 1OE is high.
17 2A4 input Data input 2A4 to the 2Y group; the output is the inverse of this input when 2OE is low.
18 1Y1 output Inverted, 3-state output of the 1A1 buffer in the first 4-bit group; high-impedance when 1OE is high.
19 2OE input Output enable 2 (active low): when low, the 2A inputs pass inverted data to the 2Y outputs; when high, outputs 2Y1-2Y4 are high-impedance.
20 VCC power_in Supply voltage pin; recommended operating range is 2 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74LV240ADWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lv240adwr-etched.step / sn74lv240adwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv240adwr.step / sn74lv240adwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 09cae063a64c3221, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF