component
SGM41511YTQF24G
Public Made by Adomby adom
SGMICRO Battery Management, TQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Contents
README
markdownSGM41511YTQF24G
SGMICRO · Battery Management · TQFN-24-EP(4x4)
SGM41511YTQF24G from SGMICRO, in a TQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VAC | input | Sense input for DC input voltage (typically from an AC/DC adaptor) that must be connected to the VBUS pin. |
| 2 | PSEL | input | Power source selection input: high sets the input current limit to 500mA (USB 2.0) and low sets it to 2.4A (adaptor), and the host can later overwrite IINDPM over I2C. |
| 3 | nPG | output | Open-drain active-low input power-good indicator that needs a 10kΩ pull-up, and goes low for a good input (UVLO < VVBUS < ACOV, above sleep threshold, ILIM > 30mA). |
| 4 | STAT | output | Open-drain charge status output needing a 10kΩ pull-up (or LED and resistor), low during charge, high when complete or in sleep, and 1Hz 50% pulses on charge suspend. |
| 5 | SCL | input | I2C clock signal that requires a 10kΩ pull-up to the logic high rail. |
| 6 | SDA | bidirectional | I2C data signal that requires a 10kΩ pull-up to the logic high rail. |
| 7 | nINT | output | Open-drain active-low interrupt output that needs a 10kΩ pull-up and sends a negative 256µs pulse to inform the host of a status update or fault. |
| 8 | NC | unconnected | Do not connect; leave this pin floating. |
| 9 | nCE | input | Active-low charge enable input; battery charging is enabled when the CHG_CONFIG bit is 1 and nCE is pulled low. |
| 10 | NC | unconnected | Do not connect; leave this pin floating. |
| 11 | TS | input | Analog temperature qualification input for the battery NTC (JEITA profile) that suspends charging when TS is outside the programmed window; 103AT-2 thermistor recommended, or a 10kΩ/10kΩ divider from REGN to GND if unused. |
| 12 | nQON | input | BATFET enable/reset control input with internal pull-up, where a low pulse of tSHIPMODE (1s TYP) exits ship mode and a low pulse of tQON_RST (16s TYP) resets the system when VBUS is absent. |
| 13 | BAT | power_in | Battery positive terminal, which needs a 10µF capacitor between BAT and GND placed close to the device. |
| 14 | BAT | power_in | Battery positive terminal, which needs a 10µF capacitor between BAT and GND placed close to the device. |
| 15 | SYS | power_out | Connection point to the converter output that powers the system, requiring a 20µF capacitor from SYS to GND close to the device in addition to COUT. |
| 16 | SYS | power_out | Connection point to the converter output that powers the system, requiring a 20µF capacitor from SYS to GND close to the device in addition to COUT. |
| 17 | GND | power_in | Ground pin of the device. |
| 18 | GND | power_in | Ground pin of the device. |
| 19 | SW | output | Switching node output that connects to the output inductor, with a 47nF bootstrap capacitor from SW to BTST. |
| 20 | SW | output | Switching node output that connects to the output inductor, with a 47nF bootstrap capacitor from SW to BTST. |
| 21 | BTST | power_in | High-side driver positive supply tied to the bootstrap diode cathode, requiring a 47nF ceramic capacitor from SW to BTST. |
| 22 | REGN | power_out | LDO output powering the LSFET driver and internal circuits, requiring a 4.7µF (10V rating) ceramic capacitor to GND and typically 4.5V to 5V. |
| 23 | PMID | power_out | Actual higher-voltage converter port connected to the RBFET and HSFET drains, requiring a 10µF ceramic capacitor to GND for high-frequency decoupling. |
| 24 | VBUS | power_in | Charger input (VIN) with a 3.9V to 13.5V operating range and 20V absolute maximum, requiring a 1µF ceramic capacitor to GND close to the device. |
| 25 | GND | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SGMICRO |
| Package | TQFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VAC, VBUS voltage (converter not switching) | VAC, VBUS | -2 | 20 | V | Converter not switching | 3 | |
| BTST, PMID voltage | BTST, PMID | -0.3 | 20 | V | Converter not switching | 3 | |
| SW voltage | SW | -2 | 16 | V | 3 | ||
| SW peak voltage | SW | -3 | 16 | V | Peak for 10ns duration | 3 | |
| BTST to SW voltage | BTST-SW | -0.3 | 6 | V | 3 | ||
| REGN, TS, nCE, nPG, BAT, SYS voltage | -0.3 | 6 | V | Converter not switching | 3 | ||
| PSEL, SDA, SCL, nINT, nQON, STAT voltage | -0.3 | 6 | V | 3 | |||
| STAT output sink current | 6 | mA | 3 | ||||
| nINT output sink current | 6 | mA | 3 | ||||
| VAC, VBUS voltage (maximum duration) | VAC, VBUS | 28 | V | Max for 10 seconds (note 1) | 3 | ||
| Junction temperature | 150 | ℃ | 3 | ||||
| Storage temperature range | -65 | 150 | ℃ | 3 | |||
| Lead temperature (soldering) | 260 | ℃ | Soldering, 10s | 3 | |||
| Input voltage range (VBUS) | VVBUS | 3.9 | 13.5 | V | 3 | ||
| Input current (VBUS) | IIN | 3.25 | A | 3 | |||
| Output DC current (SW) | ISWOP | 3.25 | A | 3 | |||
| Battery voltage | VBATOP | 4.624 | V | 3 | |||
| Fast charging current | IBATOP | 3 | A | 3 | |||
| Discharging current (continuous) | IBATOP | 6 | A | 3 | |||
| Operating temperature range | -40 | 85 | ℃ | 3 | |||
| Package thermal resistance, junction-to-ambient (TQFN-4×4-24L) | θJA | 37 | ℃/W | 3 | |||
| Package thermal resistance, junction-to-case (TQFN-4×4-24L) | θJC | 24 | ℃/W | 3 | |||
| VBUS UVLO to have active I2C (no battery), seen by VAC pin | VVAC_UVLOZ | 3.25 | 3.8 | V | +25℃; VVAC rising | 5 | |
| VAC over-voltage rising threshold (6.5V setting) | VVAC_OV_RISE | 6.15 | 6.5 | 6.95 | V | Full; VVAC rising, OVP[1:0] = 01 | 5 |
| VAC over-voltage rising threshold (10.5V setting) | VVAC_OV_RISE | 10 | 10.5 | 11.05 | V | Full; VVAC rising, OVP[1:0] = 10 | 5 |
| VAC over-voltage rising threshold (14V setting) | VVAC_OV_RISE | 13.2 | 14 | 14.55 | V | Full; VVAC rising, OVP[1:0] = 11 | 5 |
| Sleep mode falling threshold | VSLEEP | 15 | 70 | 125 | mV | +25℃; (VVAC - VBAT), VVBUSMIN_FALL ≤ VBAT ≤ VREG, VVAC falling | 5 |
| Sleep mode rising threshold | VSLEEPZ | 150 | 200 | 260 | mV | +25℃; (VVAC - VBAT), VVBUSMIN_FALL ≤ VBAT ≤ VREG, VVAC rising | 5 |
| Bad adapter detection (VBUS voltage drop) falling threshold | VVBUSMIN_FALL | 3.35 | 3.5 | 3.65 | V | Full; VVBUS falling | 5 |
| Minimum DC system voltage output | VSYS_MIN | 3.5 | 3.69 | V | Full; ISYS = 0A, VBAT < SYS_MIN[2:0] = 101 (3.5V), BATFET_DIS = 1 | 6 | |
| Maximum DC system voltage output | VSYS_MAX | 4.37 | 4.45 | 4.54 | V | Full; ISYS = 0A, VBAT ≤ 4.4V, VBAT > VSYS_MIN = 3.5V, BATFET_DIS = 1 | 6 |
| Top reverse blocking MOSFET on-resistance (VBUS to PMID, Q1) | RON_RBFET | 41 | mΩ | +25℃ | 6 | ||
| Top switching MOSFET on-resistance (PMID to SW, Q2) | RON_HSFET | 45 | mΩ | +25℃; VREGN = 5V | 6 | ||
| Bottom switching MOSFET on-resistance (SW to GND, Q3) | RON_LSFET | 55 | mΩ | +25℃; VREGN = 5V | 6 | ||
| BATFET MOSFET on-resistance (BAT to SYS) | RON_BATFET | 28 | 38 | mΩ | +25℃; VBAT = 4.2V, measured from BAT pin to SYS pin | 6 | |
| Charge voltage program range | VBAT_REG_RANGE | 3.856 | 4.624 | V | Full | 6 | |
| Charge voltage setting (VREG = 01011, 4.208V) | VBAT_REG | 4.184 | 4.208 | 4.232 | V | Full; VREG[4:0] = 01011 (4.208V) | 6 |
| Charge voltage setting (VREG = 01111, 4.352V) | VBAT_REG | 4.323 | 4.349 | 4.375 | V | Full; VREG[4:0] = 01111 (4.352V) | 6 |
| Charge voltage setting accuracy | VBAT_REG_ACC | -0.6 | 0.6 | % | Full; VBAT_REG = 4.208V or VBAT_REG = 4.352V | 6 | |
| Charge current regulation range | ICHG_REG_RANGE | 0 | 3000 | mA | Full | 6 | |
| Charge current regulation setting (ICHG = 1.38A) | ICHG_REG | 1.312 | 1.38 | 1.418 | A | +25℃; VBAT = 3.5V, ICHG = 1.38A | 6 |
| Charge current regulation setting (ICHG = 720mA) | ICHG_REG | 0.609 | 0.72 | 0.768 | A | +25℃; VBAT = 3.5V, ICHG = 720mA | 6 |
| Charge current regulation setting (ICHG = 240mA) | ICHG_REG | 0.168 | 0.24 | 0.297 | A | +25℃; VBAT = 3.5V, ICHG = 240mA | 6 |
| Pre-charge current regulation setting | IPRECHG | 130 | 175 | 222 | mA | +25℃; IPRECHG[3:0] = 0010 (180mA) | 6 |
| Termination current regulation setting | ITERM | 142 | 180 | 218 | mA | +25℃; VBAT_REG = 4.208V, ITERM[3:0] = 0010 (180mA) | 6 |
| Input current regulation limit (IINDPM 500mA) | IINDPM | 460 | 520 | mA | +25℃; VVBUS = 5V, current pulled from SW, IINDPM[4:0] = 00100 (500mA) | 7 | |
| Input current regulation limit (IINDPM 1.5A) | IINDPM | 1260 | 1570 | mA | +25℃; VVBUS = 5V, current pulled from SW, IINDPM[4:0] = 01110 (1.5A) | 7 | |
| Input voltage regulation limit (VINDPM 3.9V) | VINDPM | 3.76 | 3.87 | 3.98 | V | +25℃; VINDPM[3:0] = 0000 (3.9V) | 7 |
| Input voltage regulation limit (VINDPM 4.4V) | VINDPM | 4.24 | 4.36 | 4.48 | V | +25℃; VINDPM[3:0] = 0110 (4.4V) | 7 |
| Battery over-voltage threshold (rising, % of VBAT_REG) | VBATOVP_RISE | 103 | 104 | 105.5 | % | +25℃; VBAT rising, as percentage of VBAT_REG | 7 |
| Junction temperature regulation threshold (TREG = 1) | TJUNCTION_REG | 120 | ℃ | Full; temperature increasing, TREG = 1 (120℃) | 7 | ||
| Thermal shutdown rising temperature | TSHUT | 150 | ℃ | Full; temperature increasing | 7 | ||
| PWM switching frequency (buck mode) | fSW | 1400 | 1500 | 1600 | kHz | +25℃; oscillator frequency, buck mode | 8 |
| Boost mode regulation voltage | VOTG_REG | 5.015 | 5.185 | 5.355 | V | Full; VBAT = 3.8V, IPMID = 0A, BOOSTV[1:0] = 10 (5.15V) | 8 |
| OTG over-voltage threshold (rising) | VOTG_OVP | 5.89 | 6.015 | 6.14 | V | Full; rising threshold | 8 |
| REGN LDO output voltage (VVBUS = 9V) | VREGN | 4.75 | 5 | 5.25 | V | Full; VVBUS = 9V, IREGN = 40mA | 8 |
| REGN LDO output voltage (VVBUS = 5V) | VREGN | 4.35 | 4.65 | 4.95 | V | Full; VVBUS = 5V, IREGN = 20mA | 8 |
| Input low threshold (nCE) | VIL | 0.3 | V | Full | 8 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 1. Place the input capacitor between PMID and GND pins as close as possible to the chip with shortest copper connections | 38 |
CAD (KiCad official)
- Symbol:
SGM41511YTQF24G - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: TQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
sgm41511ytqf24g-etched.step/sgm41511ytqf24g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sgm41511ytqf24g.step/sgm41511ytqf24g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SGMICRO datasheet (41 pp, sha256
e5757ab3989215f5, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).