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Contents

README

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SN74HC373NSDTR

XBLW · Latches · SOIC-20-208mil

SN74HC373NSDTR from XBLW, in a SOIC-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-LOW 3-state output enable input; a HIGH on OE causes all outputs to assume a high-impedance OFF-state regardless of LE or D inputs.
2 Q0 tri_state 3-state latch output for bit 0; transparent to D0 when LE is HIGH and OE is LOW; latches data when LE goes LOW; high-impedance when OE is HIGH.
3 D0 input Data input for latch 0; entered into latch when LE is HIGH; stored at the HIGH-to-LOW transition of LE.
4 D1 input Data input for latch 1; entered into latch when LE is HIGH; stored at the HIGH-to-LOW transition of LE.
5 Q1 tri_state 3-state latch output for bit 1; transparent to D1 when LE is HIGH and OE is LOW; latches data when LE goes LOW; high-impedance when OE is HIGH.
6 Q2 tri_state 3-state latch output for bit 2; transparent to D2 when LE is HIGH and OE is LOW; latches data when LE goes LOW; high-impedance when OE is HIGH.
7 D2 input Data input for latch 2; entered into latch when LE is HIGH; stored at the HIGH-to-LOW transition of LE.
8 D3 input Data input for latch 3; entered into latch when LE is HIGH; stored at the HIGH-to-LOW transition of LE.
9 Q3 tri_state 3-state latch output for bit 3; transparent to D3 when LE is HIGH and OE is LOW; latches data when LE goes LOW; high-impedance when OE is HIGH.
10 GND power_in Ground supply reference, 0V.
11 LE input Active-HIGH latch enable input; when HIGH, latches are transparent and outputs follow D inputs; when LOW, data present at the inputs a set-up time before the HIGH-to-LOW transition is stored.
12 Q4 tri_state 3-state latch output for bit 4; transparent to D4 when LE is HIGH and OE is LOW; latches data when LE goes LOW; high-impedance when OE is HIGH.
13 D4 input Data input for latch 4; entered into latch when LE is HIGH; stored at the HIGH-to-LOW transition of LE.
14 D5 input Data input for latch 5; entered into latch when LE is HIGH; stored at the HIGH-to-LOW transition of LE.
15 Q5 tri_state 3-state latch output for bit 5; transparent to D5 when LE is HIGH and OE is LOW; latches data when LE goes LOW; high-impedance when OE is HIGH.
16 Q6 tri_state 3-state latch output for bit 6; transparent to D6 when LE is HIGH and OE is LOW; latches data when LE goes LOW; high-impedance when OE is HIGH.
17 D6 input Data input for latch 6; entered into latch when LE is HIGH; stored at the HIGH-to-LOW transition of LE.
18 D7 input Data input for latch 7; entered into latch when LE is HIGH; stored at the HIGH-to-LOW transition of LE.
19 Q7 tri_state 3-state latch output for bit 7; transparent to D7 when LE is HIGH and OE is LOW; latches data when LE goes LOW; high-impedance when OE is HIGH.
20 VCC power_in Positive supply voltage, recommended operating range 2.0V to 6.0V, absolute maximum −0.5V to +7.0V.

Key specifications

Parameter Value
Manufacturer XBLW
Package SOIC-20-208mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74HC373NSDTR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74hc373nsdtr-etched.step / sn74hc373nsdtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc373nsdtr.step / sn74hc373nsdtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XBLW datasheet (20 pp, sha256 db32ab70148c9cf4, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-4-6 (vision), consensus claude-opus-4-7 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF