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UCC27735QDRQ1

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Texas Instruments , SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

markdown

UCC27735QDRQ1

Texas Instruments · IC · SOIC-14

UCC27735QDRQ1 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 HI input Logic input for high-side driver; if HI is unbiased or floating, HO is held low.
2 LI input Logic input for low-side driver; if LI is unbiased or floating, LO is held low.
3 VSS power_in Logic ground.
4 EN/NC input Enable input for both drivers; biased low disables HO and LO regardless of HI and LI, biased high or floating enables both.
5 COM power_in Return for the low-side driver output; on UCC27735 it is separate from VSS (VSS-COM rated -7V to 6V).
6 LO output Low-side driver output.
7 VDD power_in Bias supply input (10V to 21V VDD-VSS) for the input logic and low-side driver output, bypassed to VSS with a typical 1µF capacitor, and to COM with 100nF if a shunt resistor is used between COM and VSS.
8 NC unconnected No connection.
9 NC unconnected No connection.
10 NC unconnected No connection.
11 HS passive Return for the high-side floating supply (switch node), rated up to 700V absolute maximum.
12 HO output High-side driver output.
13 HB power_in High-side floating supply (up to 700V absolute maximum), bypassed to HS with a capacitor typically 10× the gate capacitance for bootstrap operation.
14 NC unconnected No connection.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
HI, LI, EN input voltage -6 23 V with respect to VSS 5
VDD supply voltage VDD -0.3 23 V 5
VDD-VSS VDD-VSS -0.3 23 V 5
HB voltage HB -0.3 700 V 5
HB-HS HB-HS -0.3 23 V 5
HS-VSS DC HS-VSS -18 700 V DC, at HB-HS = 15 V 5
HS-VSS transient HS-VSS -23 700 V Transient, less than 100 ns, at HB-HS = 15 V 5
VSS-COM VSS-COM -7 6 V UCC27735 only 5
Offset supply voltage transient dVHS/dt -200 200 V/ns Allowable offset supply voltage transient 5
Junction temperature TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
ESD HBM V(ESD) -2000 2000 V Human body model, ANSI/ESDA/JEDEC JS-001; HB, HO, HS rated 1000 V 5
ESD CDM V(ESD) -500 500 V Charged device model, JESD22-C101 5
VDD-COM supply voltage VDD-COM 6 21 V UCC27735 only 5
VDD-VSS supply voltage VDD-VSS 10 21 V 5
Driver bootstrap voltage HB-HS 10 21 V 5
HS-VSS source terminal voltage DC HS-VSS 600 V DC 5
HS-VSS source terminal voltage transient HS-VSS 650 V Transient, less than 100 ns 5
HB-VSS HB pin voltage HB-VSS 3 V HB below 3V does NOT allow the output to change state 6
HI, LI, EN input voltage -5 21 V with respect to VSS 6
VSS input logic ground VSS -5 5 V UCC27735 only 6
Ambient temperature TA -40 125 °C 6
Junction temperature TJ -40 150 °C 6
Junction-to-ambient thermal resistance RθJA 80.6 °C/W 14 pins SOIC 6
Junction-to-case (top) thermal resistance RθJC(top) 41.4 °C/W 14 pins SOIC 6
Junction-to-board thermal resistance RθJB 40.1 °C/W 14 pins SOIC 6
Junction-to-top characterization parameter ψJT 6.9 °C/W 14 pins SOIC 6
Junction-to-board characterization parameter ψJB 39.7 °C/W 14 pins SOIC 6
VDD turn-on threshold VVDD ON 8.3 9 9.7 V 8V UVLO 6
VDD turn-off threshold VVDD OFF 7.8 8.5 9.2 V 8V UVLO 6
VDD UVLO hysteresis VVDD HYS 0.6 V 8V UVLO 6
VHB-VHS turn-on threshold VVHB ON 7.6 8.3 9 V 8V UVLO 6
VHB-VHS turn-off threshold VVHB OFF 7.1 7.8 8.5 V 8V UVLO 6
VHB-VHS UVLO hysteresis VVHB HYS 0.5 V 8V UVLO 6
Total quiescent VDD to VSS and COM supply current IQDD 150 300 µA HI=LI=0 V or 5 V, DC on/off state 6
Quiescent VDD-COM supply current IQCOM 55 100 µA HI=LI=0 V or 5 V, DC on/off state 6
Quiescent VDD-VSS supply current IQVSS 110 300 µA HI=LI=0 V or 5 V, DC on/off state 6
Quiescent HB-HS supply current IQBS 85 180 µA HI=0 V or 5 V, HO in DC on/off state 6
Bootstrap supply leakage current IBL 0.1 25 µA HB=HS=700 V, VDD=COM=0 V 6
Input and enable high threshold VINH, VENH 1.7 2.1 2.5 V 6
Input and enable low threshold VINL, VENL 0.7 1 1.3 V 6
Input and enable threshold hysteresis VINHYS, VENHYS 1.1 V 7
HI, LI input low bias current IINL -5 5 µA HI, LI = 0 V 7
HI, LI input high bias current IINH 20 55 µA HI, LI = 5 V 7
Pull down resistor on HI input pin RHI 100 200 KΩ HI, LI = 5 V 7
Pull down resistor on LI input pin RLI 100 200 KΩ HI, LI = 5 V 7
LO output high voltage VDD-VLOH 225 500 mV LI = 5V, ILO=-20mA 7
HO output high voltage VHB-VHOH 225 500 mV HI = 5V, IHO=-20mA 7
LO output low voltage VLOL 20 40 mV LI = 0V, ILO=20mA 7
HO output low voltage VHOL 20 40 mV HI = 0V, IHO=20mA 7
LO, HO output pull-down resistance RLOL, RHOL 1 2 Ω ILO=IHO=20mA 7
LO, HO output pull-up resistance RLOH, RHOH 12.6 25 Ω ILO=IHO=-20mA 7
HO, LO output sink current IGPK- 4 A HI=LI=0V, HO=LO=15V, PW<10us; ensured by design 7
HO, LO output source current IGPK+ 3.5 A HI=LI=5V, HO=LO=0V, PW<10us; ensured by design 7
VLI falling to VLO falling tDLFF 32 49 ns CLOAD = 0 pF, from VINL of LI to 90% of LO falling 7
VHI falling to VHO falling tDHFF 32 49 ns CLOAD = 0 pF, from VINL of HI to 90% of HO falling 7
VLI rising to VLO rising tDLRR 32 49 ns CLOAD = 0 pF, from VINH of LI to 10% of LO rising 7
VHI rising to VHO rising tDHRR 32 49 ns CLOAD = 0 pF, from VINH of HI to 10% of HO rising 7
VEN falling to VLO falling tDLFF_SD 32 49 ns CLOAD = 0 pF, from VENL of EN to 90% of LO falling 7
VEN falling to VHO falling tDHFF_SD 32 49 ns CLOAD = 0 pF, from VENL of EN to 90% of HO falling 7
VEN rising to VLO rising tDLRR_EN 32 49 ns CLOAD = 0 pF, from VENH of EN to 10% of LO rising 7
VEN rising to VHO rising tDHRR_EN 32 49 ns CLOAD = 0 pF, from VENH of EN to 10% of HO rising 7
Delay matching HI OFF, LI ON tMON 5 ns TJ = 25°C, /tDHFF, tDLRR/ 7
Delay matching HI OFF, LI ON tMON 6 ns TJ = -40°C to 150°C, /tDHFF, tDLRR/ 7
Delay matching LI OFF, HI ON tMOFF 5 ns TJ = 25°C, /tDLFF, tDHRR/ 7
Delay matching LI OFF, HI ON tMOFF 6 ns TJ = -40°C to 150°C, /tDLFF, tDHRR/ 7
Minimum HI/LI ON pulse that changes output state tON 11 20 ns 0 V to 5 V input signal on HI & LI pins, CLOAD = 1nF 8
Minimum HI/LI OFF pulse that changes output state tOFF 11 20 ns 5 V to 0 V input signal on HI & LI pins, CLOAD = 1nF 8

CAD (KiCad official)

  • Symbol: UCC27735QDRQ1
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: ucc27735qdrq1-etched.step / ucc27735qdrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc27735qdrq1.step / ucc27735qdrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (40 pp, sha256 04c832fde7f35be6, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF