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SN74LVTH126PWR
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LVTH126PWR
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-14
SN74LVTH126PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Active-low output enable for buffer 1; when OE is low the 1Y output is in the high-impedance state, and it should be tied to GND through a pulldown resistor to keep the output high-impedance above 1.5 V. |
| 2 | 1A | input | Data input of buffer 1 with active bus-hold that holds an unused or undriven input at a valid logic state, and the input accepts up to 5.5 V. |
| 3 | 1Y | tri_state | 3-state output of buffer 1 that is high-impedance when 1OE is low and is held high-impedance during power up and power down. |
| 4 | 2OE | input | Active-low output enable for buffer 2; when OE is low the 2Y output is in the high-impedance state. |
| 5 | 2A | input | Data input of buffer 2 with active bus-hold that holds an unused or undriven input at a valid logic state, and the input accepts up to 5.5 V. |
| 6 | 2Y | tri_state | 3-state output of buffer 2 that is high-impedance when 2OE is low and is held high-impedance during power up and power down. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 3Y | tri_state | 3-state output of buffer 3 that is high-impedance when 3OE is low and is held high-impedance during power up and power down. |
| 9 | 3A | input | Data input of buffer 3 with active bus-hold that holds an unused or undriven input at a valid logic state, and the input accepts up to 5.5 V. |
| 10 | 3OE | input | Active-low output enable for buffer 3; when OE is low the 3Y output is in the high-impedance state. |
| 11 | 4Y | tri_state | 3-state output of buffer 4 that is high-impedance when 4OE is low and is held high-impedance during power up and power down. |
| 12 | 4A | input | Data input of buffer 4 with active bus-hold that holds an unused or undriven input at a valid logic state, and the input accepts up to 5.5 V. |
| 13 | 4OE | input | Active-low output enable for buffer 4; when OE is low the 4Y output is in the high-impedance state. |
| 14 | VCC | power_in | Supply voltage, specified from 2.7 V to 3.6 V for recommended operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74LVTH126PWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74lvth126pwr-etched.step/sn74lvth126pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lvth126pwr.step/sn74lvth126pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
070c3051637a66df, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).