component
1EDN7511B
Public Made by Adomby adom
Infineon Technologies Gate Drive ICs, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown1EDN7511B
Infineon Technologies · Gate Drive ICs · SOT-23-6
1EDN7511B from Infineon Technologies, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply voltage with an operating range of 4.5 V to 20 V (absolute maximum 22 V). |
| 2 | OUT_SRC | output | Driver output source: low-impedance output with source capability (typically 4 A source current). |
| 3 | OUT_SNK | output | Driver output sink: low-impedance output with sink capability (typically 8 A sink current). |
| 4 | GND | power_in | Ground. |
| 5 | IN- | input | Inverting logic input; if IN- is high or left open, it causes OUT low. |
| 6 | IN+ | input | Non-inverting logic input; if IN+ is low or left open, it causes OUT low. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOT-23-6 |
| Category | Power Management ICs |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive supply voltage | VVDD | -0.3 | 22 | V | 12 | ||
| Voltage at pins IN+, IN- | VIN | -10 | 22 | V | 12 | ||
| Junction temperature | TJ | -40 | 150 | °C | 12 | ||
| Storage temperature | TS | -55 | 150 | °C | 12 | ||
| Supply voltage | VVDD | 4.5 | 20 | V | Min defined by UVLO | 14 | |
| Logic input voltage | VIN | -5 | 20 | V | 14 | ||
| Junction temperature | TJ | -40 | 150 | °C | Continuous operation above 125 °C may reduce life time | 14 | |
| VDD quiescent current | IVDDqu1 | 0.4 | mA | OUT = high, VVDD= 12 V | 14 | ||
| VDD quiescent current | IVDDqu2 | 0.37 | mA | OUT = low, VVDD= 12 V | 14 | ||
| UVLO turn on threshold | UVLOon | 3.9 | 4.2 | 4.5 | V | 14 | |
| UVLO turn off threshold | UVLOoff | 3.6 | 3.9 | 4.2 | V | 14 | |
| Input voltage threshold for transition LH | VINH | 1.9 | 2.1 | 2.3 | V | 15 | |
| Input voltage threshold for transition HL | VINL | 0.8 | 1 | 1.2 | V | 15 | |
| High Level (Sourcing) Output Resistance | Ron_SRC | 0.42 | 0.85 | 1.46 | Ω | ISRC = 50 mA | 15 |
| Low Level (Sinking) Output Resistance | Ron_SNK | 0.18 | 0.35 | 0.64 | Ω | ISNK = 50 mA | 15 |
| Input to output propagation delay (on) | TPDON | 15 | 19 | 25 | ns | CLOAD= 1.8 nF, VVDD= 12 V | 15 |
| Input to output propagation delay (off) | TPDOFF | 15 | 19 | 25 | ns | CLOAD= 1.8 nF, VVDD= 12 V | 15 |
| Rise Time | TRISE | 6.5 | 11 | ns | CLOAD= 1.8 nF, VVDD= 12 V | 15 | |
| Fall Time | TFAll | 4.5 | 9 | ns | CLOAD= 1.8 nF, VVDD= 12 V | 15 | |
| Minimum input pulse width that changes output state | TPW | 6 | 10 | ns | CLOAD= 1.8 nF, VVDD= 12 V | 15 | |
| UVLO threshold hysteresis | UVLOhys | 0.3 | V | 14 | |||
| Input pull up resistor | RIN H | 400 | kΩ | Inputs with initial high logic level | 15 | ||
| Input pull down resistor | RIN L | 100 | kΩ | Inputs with initial low logic level | 15 | ||
| High Level (Sourcing) Output Current | ISRC_peak | 4 | A | 15 | |||
| Low Level (Sinking) Output Current | ISNK_Peak | -8 | A | 15 | |||
| Reverse current peak at pins OUT, OUT_SRC/OUT_SNK | ISNK_rev / ISRC_rev | -5 | 5 | Apk | < 500 ns | 12 | |
| ESD capability CDM | VESD | 1.5 | kV | Charged Device Mode (CDM), JESD22-C101 | 12 | ||
| ESD capability HBM | VESD | 2.5 | kV | Human Body Model (HBM), JESD22-A114 | 12 | ||
| Thermal resistance junction-ambient | RthJA25 | 170 | K/W | PG-SOT23-6-2, Tamb=25°C | 12 | ||
| Thermal resistance junction-case (top) | RthJC25 | 81 | K/W | PG-SOT23-6-2, Tamb=25°C | 12 | ||
| Thermal resistance junction-board | RthJB25 | 52 | K/W | PG-SOT23-6-2, Tamb=25°C | 12 | ||
| Characterization parameter junction-case (top) | ΨthJC25 | 14 | K/W | PG-SOT23-6-2, Tamb=25°C | 12 | ||
| Characterization parameter junction-board | ΨthJB25 | 51 | K/W | PG-SOT23-6-2, Tamb=25°C | 13 |
CAD (KiCad official)
- Symbol:
1EDN7511B - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
1edn7511b-etched.step/1edn7511b-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);1edn7511b.step/1edn7511b.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (28 pp, sha256
c95947dd37af42d4, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).