component
F280023PTSR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownF280023PTSR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
F280023PTSR from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO29 | bidirectional | General Purpose I/O 29; configurable as input or output with programmable pull-up, supporting SCI transmit, ePWM output, or other peripheral functions |
| 2 | GPIO28 | bidirectional | General Purpose I/O 28; configurable as input or output with programmable pull-up, supporting SCI receive, ePWM output, or other peripheral functions |
| 3 | XRSn | bidirectional | Device reset input (active low) and watchdog reset output with open-drain configuration; external 2.2kΩ to 10kΩ pull-up to VDDIO with optional 100nF capacitor to VSS for noise filtering |
| 4 | A6, C6 | input | Analog input pins for ADC channels serving as ADC-A input 6 and ADC-C input 6 (or general analog inputs); support single-ended signal mode from VREFLO to VREFHI range |
| 5 | A3/C5/VDAC | input | Dual ADC analog inputs (A3/ADC-A input 3, C5/ADC-C input 5) and optional external reference voltage for on-chip CMPSS DAC with internal capacitor to VSSA; minimum 1µF external capacitor required when used as CMPSS DAC reference |
| 6 | A2/C9 | input | ADC analog inputs (A2/ADC-A input 2, C9/ADC-C input 9) supporting single-ended signal mode from VREFLO to VREFHI range |
| 7 | A15/C7 | input | ADC analog inputs (A15/ADC-A input 15, C7/ADC-C input 7) supporting single-ended signal mode from VREFLO to VREFHI range |
| 8 | A11/C0 | input | ADC analog inputs (A11/ADC-A input 11, C0/ADC-C input 0) supporting single-ended signal mode from VREFLO to VREFHI range |
| 9 | A5/C2 | input | ADC analog inputs (A5/ADC-A input 5, C2/ADC-C input 2) supporting single-ended signal mode from VREFLO to VREFHI range |
| 10 | A1 | input | General analog input (ADC-A or ADC-C channel 1) accepting signals within VREFLO to VREFHI range for analog-to-digital conversion |
| 11 | A0/C15 | input | ADC analog inputs (A0/ADC-A input 0, C15/ADC-C input 15) supporting single-ended signal mode from VREFLO to VREFHI range |
| 12 | VREFHI | input | ADC high reference voltage; in external reference mode externally driven (2.4V to 3.3V nominal), in internal reference mode device-driven to 1.65V or 2.5V; minimum 2.2µF capacitor required between VREFHI and VREFLO |
| 13 | VREFLO | passive | ADC low reference voltage internally connected to VSSA, providing 0V reference ground for ADC single-ended conversions |
| 14 | A12/C1 | input | ADC analog inputs (A12/ADC-A input 12, C1/ADC-C input 1) supporting single-ended signal mode from VREFLO to VREFHI range |
| 15 | A7/C3 | input | ADC analog inputs (A7/ADC-A input 7, C3/ADC-C input 3) supporting single-ended signal mode from VREFLO to VREFHI range |
| 16 | A8/C11 | input | ADC analog inputs (A8/ADC-A input 8, C11/ADC-C input 11) supporting single-ended signal mode from VREFLO to VREFHI range |
| 17 | VSSA | power_in | Analog ground reference for ADC and analog modules; must be connected to digital ground VSS with minimum 2.2µF capacitor on VDDA for decoupling |
| 18 | VDDA | power_in | 3.3V analog power supply for ADC, temperature sensor, CMPSS, and analog modules; minimum 2.2µF decoupling capacitor required near pin |
| 19 | A4/C14 | input | ADC analog inputs (A4/ADC-A input 4, C14/ADC-C input 14) supporting single-ended signal mode from VREFLO to VREFHI range |
| 20 | A9/C8 | input | ADC analog inputs (A9/ADC-A input 9, C8/ADC-C input 8) supporting single-ended signal mode from VREFLO to VREFHI range |
| 21 | A10/C10 | input | ADC analog inputs (A10/ADC-A input 10, C10/ADC-C input 10) supporting single-ended signal mode from VREFLO to VREFHI range |
| 22 | VSS | power_in | Digital ground connection; all VSS pins must be connected to circuit board ground for proper signal return path and noise immunity |
| 23 | GPIO13 | bidirectional | General Purpose I/O 13; configurable as input or output with programmable pull-up, supporting ePWM, eQEP, CMPSS, SPI, I2C, and other peripheral functions |
| 24 | GPIO12 | bidirectional | General Purpose I/O 12; configurable as input or output with programmable pull-up, supporting ePWM, eQEP, PMBus, LIN, SPI, and other peripheral functions |
| 25 | GPIO33 | bidirectional | General Purpose I/O 33; configurable as input or output with programmable pull-up, supporting I2C, SPI, LIN, eQEP, ADC start-of-conversion, and other peripheral functions |
| 26 | GPIO16 | bidirectional | General Purpose I/O 16; configurable as input or output with programmable pull-up, supporting SPI, ePWM, eQEP, PMBus, XCLKOUT, and other peripheral functions |
| 27 | GPIO24 | bidirectional | General Purpose I/O 24; configurable as input or output with programmable pull-up, supporting output X-BAR, eQEP, SPI, PMBus, LIN, I2C, and error status output functions |
| 28 | TCK | input | JTAG test clock input with internal pull-up resistor; minimum 66.66ns period for JTAG protocol compatibility and timing requirements |
| 29 | GPIO37/TDO | tri_state | General Purpose I/O 37 or JTAG Test Data Output; when configured as JTAG TDO, operates in tri-state mode during inactive periods, requiring internal or external pull-up resistor to prevent floating input |
| 30 | TMS | bidirectional | JTAG Test Mode Select input with internal pull-up resistor; external 2.2kΩ pull-up to VDDIO recommended for normal operation to keep JTAG interface in reset state |
| 31 | GPIO35/TDI | input | General Purpose I/O 35 or JTAG Test Data Input; when configured as JTAG TDI, default multiplexer selection with optional internal pull-up resistor or external 1kΩ to 100kΩ pull-up recommended to prevent floating input |
| 32 | GPIO32 | bidirectional | General Purpose I/O 32; configurable as input or output with programmable pull-up, supporting I2C, SPI, LIN, eQEP, FSI, ADC start-of-conversion, and other peripheral functions |
| 33 | GPIO18_X2 | output | General Purpose I/O 18 or Crystal oscillator output (X2); in crystal mode provides output for parallel-resonant quartz crystal or ceramic resonator circuit |
| 34 | GPIO19_X1 | input | General Purpose I/O 19 or Crystal oscillator input (X1); in crystal mode accepts input from quartz crystal or single-ended 3.3V logic-level clock signal with 50% duty cycle |
| 35 | VDDIO | power_in | 3.3V digital I/O power supply for GPIO, digital peripherals, JTAG, and I/O buffers; minimum 0.1µF capacitor per pin or consolidated decoupling capacitor required |
| 36 | VDD | power_in | 1.2V digital core power supply for CPU, memory, and internal logic, generated from VDDIO via internal VREG; minimum total 10-22µF capacitor required with distributed decoupling at each pin |
| 37 | VSS | power_in | Digital ground connection; all VSS pins must be connected to circuit board ground for proper signal return path and noise immunity |
| 38 | GPIO4 | bidirectional | General Purpose I/O 4; configurable as input or output with programmable pull-up, supporting ePWM, eQEP, SPI, CAN, FSI, CLB, and other peripheral functions |
| 39 | GPIO3 | bidirectional | General Purpose I/O 3; configurable as input or output with programmable pull-up, supporting ePWM, SPI, SCI, CAN, PMBus, I2C, output X-BAR, and other peripheral functions |
| 40 | GPIO2 | bidirectional | General Purpose I/O 2; configurable as input or output with programmable pull-up, supporting ePWM, output X-BAR, PMBus, SPI, SCI, CAN, I2C, and other peripheral functions |
| 41 | GPIO1 | bidirectional | General Purpose I/O 1; configurable as input or output with programmable pull-up, supporting ePWM, I2C, SPI, eQEP, output X-BAR, and other peripheral functions |
| 42 | GPIO0 | bidirectional | General Purpose I/O 0; configurable as input or output with programmable pull-up, supporting ePWM, I2C, SPI, FSI, CLB output X-BAR, and other peripheral functions |
| 43 | GPIO7 | bidirectional | General Purpose I/O 7; configurable as input or output with programmable pull-up, supporting ePWM, output X-BAR, eQEP, SPI, FSI, CLB, and other peripheral functions |
| 44 | VSS | power_in | Digital ground connection; all VSS pins must be connected to circuit board ground for proper signal return path and noise immunity |
| 45 | VDD | power_in | 1.2V digital core power supply for CPU, memory, and internal logic, generated from VDDIO via internal VREG; minimum total 10-22µF capacitor required with distributed decoupling at each pin |
| 46 | VDDIO | power_in | 3.3V digital I/O power supply for GPIO, digital peripherals, JTAG, and I/O buffers; minimum 0.1µF capacitor per pin or consolidated decoupling capacitor required |
| 47 | GPIO5 | bidirectional | General Purpose I/O 5; configurable as input or output with programmable pull-up, supporting ePWM, output X-BAR, CAN, SPI, LIN, FSI, CLB, and other peripheral functions |
| 48 | GPIO6 | bidirectional | General Purpose I/O 6; configurable as input or output with programmable pull-up, supporting ePWM, output X-BAR, SPI, LIN, FSI, CLB SYNCOUT, and other peripheral functions |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
CAD (KiCad official)
- Symbol:
F280023PTSR - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
f280023ptsr-etched.step/f280023ptsr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);f280023ptsr.step/f280023ptsr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (245 pp, sha256
0723d8e3e09e1f8b, retrieved 2026-10-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).