NCP12510ASN65T1G from onsemi, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	The controller ground.
2	FB	input	Hooking an optocoupler collector to this pin will allow regulation.
3	OPP/Latch	input	A resistive divider from the auxiliary winding to this pin sets the OPP compensation level during the on-time, and when the voltage exceeds a certain level at turn off the part is fully latched off.
4	CS	input	This pin monitors the primary peak current but also offers a means to introduce slope compensation.
5	VCC	power_in	This pin is connected to an external auxiliary voltage, and when the VCC exceeds a certain level the part enters an auto-recovery hiccup.
6	DRV	output	The driver output drives an external MOSFET gate.

Key specifications

Parameter	Value
Manufacturer	onsemi
Package	SOT-23-6
Category	Power Management ICs
Pins	6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Power Supply voltage, VCC pin, continuous voltage	VCC	-0.3		35	V		4
Maximum sourced current, pulsed width < 800 ns	Isource,max			0.6	A	Pulsed width < 800 ns	4
Maximum sinked current, pulse width < 800 ns	Isink,max			1	A	Pulse width < 800 ns	4
Maximum negative transient voltage on OPP pin	VOPP(tran)			-1	V	Note 2	4
Maximum injected negative current into the OPP pin (pin 3)	IOPP			-2	mA		4
Power Supply voltage range CS, FB and OPP low power pins	VCS, VFB, VOPP	-0.3		5.5	V	Maximum voltage on low power pins CS, FB and OPP (Note 2)	4
Maximum Junction Temperature	TJ,max			150	°C		4
Storage Temperature Range		-60		150	°C		4
Human Body Model ESD Capability (all pins)	HBM		4		kV	per JEDEC JESD22-A114F	4
Charged-Device Model ESD Capability	CDM		750		V	per JEDEC JESD22-C101E	4
Thermal Resistance Junction-to-Air	RθJ−A		360		°C/W		4
VCC increasing level at which driving pulses are authorized	VCC(on)	16	18	20	V		5
VCC decreasing level at which driving pulses are stopped	VCC(min)	8.3	8.9	9.5	V		5
Hysteresis VCC(on), VCC(min)	VCC(hyst)	7.7			V		5
Defined hysteresis between minimum and reset voltage VCC(min), VCC(reset)	VCC(reset_hyst)	0.15	0.3	0.45	V		5
Start-up current	ICC1		6	10	µA	VCC(on), 100 mV	5
Internal IC consumption 65 kHz	ICC2		1	1.4	mA	VFB = 3.2 V, fSW = 65 kHz and CL = 0 nF	5
Internal IC consumption 65 kHz with load	ICC3		1.7	2.7	mA	VFB = 3.2 V, fSW = 65 kHz and CL = 1 nF	5
Internal consumption in skip mode, non switching	ICC(no-load)		300		µA	VFB = 0 V	5
Internal consumption in fault during going-down VCC	ICC(fault)	300	370		µA	VCC, VFB = 4 V	5
Internal IC consumption in skip mode for 65 kHz version	ICC(standby)		420		µA	VCC = 14 V, driving a typical 7-A/600-V MOSFET, includes opto current (Note 4)	5
DRV pin level at VCC = VCC(min) + 100 mV with a 33 k resistor to GND	VDRV(low)	8			V	VCC = VCC(min) + 100 mV with a 33 k resistor to GND	5
DRV pin level at VCC = VOVP, 100 mV (DRV unloaded)	VDRV(high)	10	12	14	V	DRV unloaded	5
Output voltage rise-time	tr		40		ns	@ CL = 1 nF, 10-90% of output signal	5
Output voltage fall-time	tf		30		ns	@ CL = 1 nF, 10-90% of output signal	5
Source resistance	ROH		28		Ω	VCC = 12 V, IDRV = 100 mA	5
Sink resistance	ROL		7		Ω	VCC = 12 V, IDRV = 100 mA	5
Peak source current	Isource		300		mA	VGS = 0 V	5
Peak sink current	Isink		500		mA	VGS = 12 V	5
Maximum internal current set point TJ = 25°C	Vlimit	0.744	0.8	0.856	V	TJ = 25°C, pin 3 grounded	5
Maximum internal current set point TJ = −40°C to 125°C	Vlimit	0.72	0.8	0.88	V	TJ = −40°C to 125°C, pin 3 grounded	5
Propagation delay from CS pin to DRV output	tDEL		50	80	ns		5
Internal voltage setpoint for frequency foldback trip point	VCS(fold)		475		mV	59% of Vlimit	5
Internal peak current setpoint freeze	VCS(freeze)		250		mV	≈31% of Vlimit	5
Leading Edge Blanking Duration	tLEB		300		ns		5
Internal soft-start duration	tSS		4		ms	activated upon startup or auto-recovery	5
Set point decrease for pin 3 grounded	IOPPs		0		%	pin 3 grounded	5
Set point decrease for pin 3 biased to −250 mV	IOPPo		31.3		%	pin 3 biased to −250 mV	5
Voltage set point for pin 3 biased to −250 mV, TJ = 25°C	IOOPv	0.51	0.55	0.6	V	pin 3 biased to −250 mV, TJ = 25°C	5
Voltage set point for pin 3 biased to −250 mV, TJ = −40° to 125°C	IOOPv	0.5	0.55	0.62	V	pin 3 biased to −250 mV, TJ = −40° to 125°C	5
Oscillation frequency (65 kHz version)	fOSC(nom)	61	65	71	kHz	65 kHz version	5
Maximum duty-ratio	Dmax	76	80	84	%		5
Frequency jittering in percentage of fOSC	fjitter	-5		5	%	jitter is kept even in foldback mode	5
Swing frequency	fswing		240		Hz		6
Internal equivalent feedback resistance	Req		29		kΩ		6
FB pin to current set point division ratio	Kratio		4		-		6
Feedback voltage below which the peak current is frozen	VFB(freeze)		1		V		6
Feedback voltage corresponding with maximum internal current set point	VFB(limit)		3.2		V		6
Internal pull-up voltage on FB pin	VFB(open)		4		V		6
Frequency foldback level on the FB pin	Vfold(start)		1.9		V	≈59% of maximum peak current	6
Minimum operating frequency	ftrans	22	26	30	kHz		6
End of frequency foldback feedback level	Vfold(end)		1.5		V	fsw = ftrans	6
Skip-cycle level voltage on the feedback pin	Vskip		0.8		V		6
Hysteresis on the skip comparator	Vskip(hyst)		50		mV		6
Latching level input on OPP/Latch pin	Vlatch	2.85	3	3.15	V		6
Blanking time after Drive output turn off	tlatch(blank)		1		s		6
OVP/OTP delay time constant before latch is confirmed	tlatch(del)		600		ns		6
Over voltage protection on the VCC pin	VOVP	24	25.5	27	V	except D version	6
Delay time constant before OVP on VCC is confirmed	tOVP(del)		20		s		6
Internal fault timer duration	tfault	100	115	130	ms		6

CAD (KiCad official)

Symbol: NCP12510ASN65T1G
Footprint: Package_TO_SOT_SMD:SOT-23-6
3D model: SOT-23-6 (KiCad packages3D, STEP)
3D model files: ncp12510asn65t1g-etched.step / ncp12510asn65t1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp12510asn65t1g.step / ncp12510asn65t1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: onsemi datasheet (28 pp, sha256 50edcb33a05dca5e, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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NCP12510ASN65T1G

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