MP9928GF-Z from Monolithic Power Systems, in a TSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN	power_in	Input supply: the MP9928 operates from a 4V to 60V input, and a ceramic capacitor is needed to prevent large voltage spikes from appearing at the input.
2	EN/SYNC	input	Enable input with a 1.22V threshold and 130mV of hysteresis, usable for external UVLO, and an applied external sync clock makes the internal clock follow the sync frequency.
3	VCC2	power_in	External power supply for the internal VCC1 regulator, which disables the VIN-derived supply when VCC2 is higher than 4.7V; do not connect more than 12V to this pin.
4	VCC1	power_out	Internal bias supply that must be decoupled with a 1µF or greater ceramic capacitor, with capacitance no more than 4.7µF.
5	SGND	power_in	Low-noise signal ground reference.
6	SS	passive	Soft-start control input, where an external capacitor from SS to SGND programs the soft-start period and is charged by an internal 4µA current source.
7	COMP	passive	Compensation pin for the regulation control loop, where an RC network is connected from COMP to GND.
8	FB	input	Feedback input to the error amplifier, where an external resistive divider from output to GND is compared to the internal +0.8V reference to set the regulation voltage.
9	CCM/AAM	input	Mode-select pin: connecting to VCC1 or floating selects CCM, while a resistor to GND giving a low level selects AAM, with the AAM voltage no less than 480mV.
10	FREQ	passive	A resistor connected between FREQ and GND sets the switching frequency.
11	PG	output	Open-drain power good output that is pulled low when the regulator output falls outside about ±10% of its nominal value.
12	ILIM	input	Current sense voltage limit select: connecting to GND sets 25mV, connecting to VCC1 sets 50mV, and floating sets 75mV at maximum output current.
13	SYNCO	output	Outputs a clock 180° out-of-phase with the internal or external sync clock in CCM or DCM (not Sleep mode) for dual-channel co-pack, and outputs a DC voltage in other cases such as Sleep mode, Low Dropout mode, and fault protections.
14	SENSE-	input	Negative input for the current sense, with the sensed inductor current limit threshold determined by the status of the ILIM pin.
15	SENSE+	input	Positive input for the current sense, with the sensed inductor current limit threshold determined by the status of the ILIM pin.
16	PGND	power_in	Power ground reference for the internal low-side switch driver and VCC1 regulator, to be connected directly to the negative terminal of the VCC1 decoupling capacitor.
17	BG	output	Bottom gate driver output that connects to the gate of the synchronous N-channel MOSFET.
18	SW	passive	Switch node that serves as the reference for the VBST supply and the high-current return for the bootstrapped switch.
19	TG	output	Top gate drive output for the top N-channel MOSFET, driven from the BST capacitor and returned to SW for a true floating drive.
20	BST	power_out	Bootstrap pin that is the positive supply for the internal floating high-side driver, with a bypass capacitor connected between BST and SW and charged from VCC1 through a diode.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Monolithic Power Systems
Package	TSSOP-20-EP
Category	Power Management (PMIC)
Pins	21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input supply voltage (VIN) absolute maximum	VIN	-0.3		65	V		3
EN/SYNC absolute maximum		-0.3		50	V		3
SW absolute maximum		-0.3		65	V	-4V for <20ns	3
BST - SW absolute maximum		-0.3		6.5	V		3
Supply voltage (VCC1) absolute maximum	VCC1	-0.3		6.5	V		3
External supply voltage (VCC2) absolute maximum	VCC2	-0.3		15	V		3
SENSE+ / - absolute maximum		-0.3		28	V		3
Differential sense (SENSE+ to SENSE-) absolute maximum		-0.7		0.7	V		3
All other pins absolute maximum		-0.3		6.5	V		3
Continuous power dissipation TSSOP-20 EP	PD			3.1	W	TA = +25°C	3
Lead temperature				260	°C		3
Storage temperature		-65		175	°C		3
Supply voltage (VIN) recommended	VIN	4		60	V		3
Output voltage (VOUT) recommended	VOUT			24	V		3
Supply voltage for (VCC2) recommended	VCC2	5		12	V		3
Operating junction temperature (TJ) recommended	TJ	-40		125	°C		3
VIN UVLO threshold (rising)	INUV_RISING	4.5		5	V		4
VIN UVLO threshold (falling)	INUV_FALLING	3.7		3.95	V		4
VIN supply current with VCC2 bias	IQ_VCC2	25		40	μA	VCC2 = 12V, external bias	4
VIN supply current without VCC2 bias	IQ	750		1000	μA	VCC2 = 0, VFB = 0.84V, VAAM = 5V, SENSE+ = SENSE- = 0.3V	4
VIN AAM current	IQ_AAM	250		350	μA	VAAM=0.6V, VFB=0.84V, SENSE+ = SENSE- = 0.3V	4
VIN shutdown current	ISHDN	0.5		3	μA	VEN = 0V	4
VCC1 regulator load regulation from VIN		1		3	%	Load = 0 to 50mA, VCC2 floating or connects to GND	4
VCC1 regulator load regulation from VCC2		1		3	%	Load = 0 to 50mA, VCC2 = 12V	4
VCC2 UVLO threshold (rising)	VCC2_RISING	4.7		4.92	V		4
VCC2 supply current	IVCC2	800		1200	μA	VAAM = 5V, VFB = 0.84V, VCC2 = 12V	4
VCC2 supply current	IVCC2	200		300	μA	VAAM = 0.6V, VFB = 0.84V, VCC2 = 12V	4
Feedback voltage (TJ=25°C)	VFB	0.792	0.8	0.808	V	4V ≤ VIN ≤ 60V, TJ=25°C	4
Feedback voltage (TJ=-40°C to 125°C)	VFB	0.788	0.8	0.812	V	4V ≤ VIN ≤ 60V, TJ=-40°C to 125°C	4
Enable threshold (rising)	VEN_RISING	1.16	1.22	1.28	V		4
Enable threshold (falling)	VEN_FALLING	1.03	1.09	1.15	V		4
Enable turn-off delay	TOFF	10		15	μs		4
Operating frequency	FSW	240	300	360	kHz	R Freq = 65kΩ	5
Sync/EN frequency range	FSYNC	100		1000	kHz		5
Current sense common mode voltage range	VSENSE+/-	0		24	V		5
Current limit sense voltage (ILIM=GND)	VILIMIT	15	25	35	mV	ILIM = GND, VSENSE+ = 3.3V	5
Current limit sense voltage (ILIM=VCC1)	VILIMIT	40	50	60	mV	ILIM = VCC1, VSENSE+ = 3.3V	5
Current limit sense voltage (ILIM=FLOAT)	VILIMIT	65	75	85	mV	ILIM = FLOAT, VSENSE+ = 3.3V	5
Soft-start source current	ISS	2	4	6	μA	SS = 0.5V	5
Error amp sink/source current	IEA	-30		30	μA	FB = 0.7/0.9V	5
Over-voltage threshold	VOV	110	115	120	% VFB		5
TG maximum duty cycle	Dmax	98		99.5	%	VFB = 0.7V	6
BG minimum on time	TON_MIN_BG	175		250	ns		6
Power good low	VPG_Low	0.1		0.3	V	ISINK = 4mA	6
PG rising threshold (VOUT rising)	PGVth_RSING	85	90	96.5	% VFB	VOUT rising	6
PG rising threshold (VOUT falling)	PGVth_RSING	101	107	112.5	% VFB	VOUT falling	6
PG falling threshold (VOUT falling)	PGVth_FALLING	81	87	92.5	% VFB	VOUT falling	6
PG falling threshold (VOUT rising)	PGVth_FALLING	105	110	116.5	% VFB	VOUT rising	6
Thermal resistance junction-to-ambient TSSOP-20 EP	θJA		40		C/W	JESD51-7, 4-layer PCB (note 5)	3
Thermal resistance junction-to-case TSSOP-20 EP	θJC		8		C/W	JESD51-7, 4-layer PCB (note 5)	3
VCC1 regulator output voltage from VIN	VCC1_VIN		5		V	VIN > 6V	4
VCC1 regulator output voltage from VCC2	VCC1_VCC2		5		V	VCC2 > 6V	4
VIN UVLO hysteresis	INUV_HYS		800		mV		4
VCC2 UVLO threshold (falling)	VCC2_FALLING		4.45		V		4
VCC2 threshold hysteresis	VCC2_HYS		250		mV		4
Feedback current	IFB		10		nA	VFB = 0.84V	4
Enable threshold hysteresis	VEN_TH		130		mV		4
Maximum programmable frequency	FSWH		1000		kHz		5
Minimum programmable frequency	FSWL		100		kHz		5

CAD (KiCad official)

Symbol: MP9928GF-Z
Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
3D model: TSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: mp9928gf-z-etched.step / mp9928gf-z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mp9928gf-z.step / mp9928gf-z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Monolithic Power Systems datasheet (25 pp, sha256 61fba8c327700363, retrieved 2026-11-05, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

MP9928GF-Z

Verified MP9928GF-Z

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3D Model

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