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Contents

README

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MCP14A1202T-E

Microchip Tech · Gate Drivers · SOIC-8

MCP14A1202T-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Bias supply input for the MOSFET driver with a stated voltage range of 4.5V to 18V, which must be decoupled to ground with a local capacitor.
2 IN input High-impedance control input with low threshold levels and hysteresis between high and low input levels for noise immunity.
3 EN input High-impedance active-high enable with low thresholds and hysteresis; driving it below threshold forces OUT low regardless of IN, and an internal pull-up lets the pin float for standard operation.
4 GND power_in Power ground return for the input and output stages, which should have a low-impedance connection to the bias supply return.
5 GND power_in Power ground return for the input and output stages, which should have a low-impedance connection to the bias supply return.
6 OUT output CMOS push-pull output that sources and sinks 12.0A peak current at VDD = 18V, with a reverse current latch-up rating of 500 mA.
7 OUT output CMOS push-pull output that sources and sinks 12.0A peak current at VDD = 18V, with a reverse current latch-up rating of 500 mA.
8 VDD power_in Bias supply input for the MOSFET driver with a stated voltage range of 4.5V to 18V, which must be decoupled to ground with a local capacitor.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Logic '1' High Input Voltage VIH 2 1.6 V 3
Logic '0' Low Input Voltage VIL 1.3 0.8 V 3
Input Current IIN -1 1 µA 0V ≤ VIN ≤ VDD 3
Logic '1' High Enable Voltage VEH 2 1.6 V 3
Logic '0' Low Enable Voltage VEL 1.3 0.8 V 3
Propagation Delay tD3 28 33 ns VDD = 18V, VEN = 5V, see Figure 4-3, (Note 1) 3
Low Output Voltage VOL 0.025 V IOUT = 0A 3
Output Resistance, High ROH 0.9 1.5 Ω IOUT = 10 mA, VDD = 18V 3
Output Resistance, Low ROL 0.6 1.2 Ω IOUT = 10 mA, VDD = 18V 3
Latch-Up Protection Withstand Reverse Current IREV 0.5 A Duty cycle ≤ 2%, t ≤ 300 µs (Note 1) 3
Rise Time tR 25 30 ns VDD = 18V, CL = 15,000 pF, see Figure 4-1, Figure 4-2 3
Fall Time tF 25 30 ns VDD = 18V, CL = 15,000 pF, see Figure 4-1, Figure 4-2 3
Delay Time tD1 28 33 ns VDD = 18V, VIN = 5V, see Figure 4-1 and Figure 4-2 4
Supply Voltage VDD 4.5 18 V 4
Power Supply Current IDD 360 600 µA VIN = 3V, VEN = 3V 4
Logic '1' High Input Voltage (over operating temperature range) VIH 2 1.6 V 4
Logic '0' Low Input Voltage (over operating temperature range) VIL 1.3 0.8 V 4
Input Current (over operating temperature range) IIN -10 10 µA 0V ≤ VIN ≤ VDD 4
Logic '1' High Enable Voltage (over operating temperature range) VEH 2 1.6 V 4
Logic '0' Low Enable Voltage (over operating temperature range) VEL 1.3 0.8 V 4
Propagation Delay (over operating temperature range) tD3 32 37 ns VDD = 18V, VEN = 5V, TA = +125°C, see Figure 4-3, (Note 1) 4
Low Output Voltage (over operating temperature range) VOL 0.025 V DC Test 4
Output Resistance, High (over operating temperature range) ROH 2 Ω IOUT = 10 mA, VDD = 18V 4
Output Resistance, Low (over operating temperature range) ROL 1.7 Ω IOUT = 10 mA, VDD = 18V 4
Rise Time (TA = +125°C) tR 30 35 ns VDD = 18V, CL = 15,000 pF, TA = +125°C, see Figure 4-1, Figure 4-2 5
Fall Time (TA = +125°C) tF 30 35 ns VDD = 18V, CL = 15,000 pF, TA = +125°C, see Figure 4-1, Figure 4-2 5
Delay Time (TA = +125°C) tD1 32 37 ns VDD = 18V, VIN = 5V, TA = +125°C, see Figure 4-1, Figure 4-2 5
Supply Voltage VDD 4.5 18 V 5
Power Supply Current (TA = +125°C) IDD 750 uA VIN = 3V, VEN = 3V 5
Specified Temperature Range TA -40 125 °C 5
Maximum Junction Temperature TJ 150 °C 5
Storage Temperature Range TA -65 150 °C 5
Supply Voltage VDD 20 V 3
Package Power Dissipation, 8L SOIC 1 W TA = +50°C 3
ESD Protection on all pins (HBM) 2 kV 3
Junction-to-Ambient Thermal Resistance, 8LD SOIC JA 99.8 °C/W Note 1 5
Junction-to-Top Characterization Parameter, 8LD SOIC JT 5.9 °C/W Note 1 5
Junction-to-Board Characterization Parameter, 8LD SOIC JB 64.8 °C/W Note 1 5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] A A2 19

CAD (KiCad official)

  • Symbol: MCP14A1202T-E
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: mcp14a1202t-e-etched.step / mcp14a1202t-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp14a1202t-e.step / mcp14a1202t-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (30 pp, sha256 29d100f19f6fdaa2, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF