AD5761RACPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RESET	input	Active-low reset input that returns the device to its default power-on state, clamping the output to ground and powering down the output buffer; an internal pull-up allows it to be left floating.
2	VREFIN/VREFOUT	bidirectional	Internal reference voltage output and external reference voltage input; 2.5 V is required for specified performance, and a 10 nF capacitor should be connected to the internal reference to minimize noise.
3	AGND	power_in	Ground reference pin for the analog circuitry.
4	VSS	power_in	Negative analog supply accepting −16.5 V to 0 V; connect to 0 V for unipolar output ranges, and it must be decoupled to AGND.
5	VOUT	output	Analog output voltage of the DAC, capable of directly driving a 2 kΩ, 1 nF load.
6	VDD	power_in	Positive analog supply accepting 4.75 V to 30 V for unipolar ranges and 4.75 V to 16.5 V for bipolar ranges; it must be decoupled to AGND.
7	DNC	unconnected	Do not connect to this pin.
8	SDO	output	Serial data output for daisy-chain or readback mode, clocked out on the rising edge of SCLK and valid on the falling edge of SCLK.
9	LDAC	input	Load DAC logic input that updates the DAC register and analog output; when held high during an input register write, the output update is deferred until the falling edge of LDAC, and an internal pull-up allows it to float.
10	SDI	input	Serial data input; data must be valid on the falling edge of SCLK.
11	SYNC	input	Active-low frame synchronization input; data is clocked in on SCLK falling edges while SYNC is low and latched on the rising edge of SYNC.
12	SCLK	input	Serial clock input at speeds of up to 50 MHz, with data clocked into the input shift register on the falling edge.
13	DVCC	power_in	Digital supply accepting 1.7 V to 5.5 V, which sets the voltage at which the digital interface operates.
14	DGND	power_in	Digital ground.
15	ALERT	output	Active-low alert asserted when the die temperature exceeds approximately 150°C or on an output short circuit or brownout, and also asserted low during power-up or software/hardware reset until a control register write sets it high.
16	CLEAR	input	Falling-edge clear input that sets the DAC register to zero scale, midscale, or full scale (user selectable) and updates the DAC output; an internal pull-up allows it to float.
17	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-16(3x3)
Category	Interface ICs
Pins	17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Relative Accuracy, INL (A Grade)	INL	-8		8	LSB	External reference3 and internal reference	3
Differential Nonlinearity, DNL	DNL	-1		1	LSB		3
Zero-Scale Error		-6		6	mV	All ranges except ±10 V and 0 V to 20 V, external reference3	3
Zero-Scale Error		-10		10	mV	0 V to 20 V, ±10 V ranges, external reference3	3
Zero-Scale Error		-8		8	mV	±5 V range, internal reference	3
Zero-Scale Error		-9		9	mV	0 V to 20 V range, internal reference	3
Zero-Scale Error		-13		13	mV	±10 V range, internal reference	3
Zero-Scale Error TC, unipolar ranges		-5		5	µV/°C	Unipolar ranges, external reference3 and internal reference	3
Zero-Scale Error TC, bipolar ranges		-15		15	µV/°C	Bipolar ranges, external reference3 and internal reference	3
Bipolar Zero Error		-5		5	mV	All bipolar ranges except ±10 V	3
Bipolar Zero Error		-7		7	mV	±10 V output range	3
Bipolar Zero TC		-2		2	µV/°C	±3 V range, external reference3 and internal reference	3
Bipolar Zero TC		-5		5	µV/°C	All bipolar ranges except ±3 V range, external reference3 and internal reference	3
Offset Error		-6		6	mV	All ranges except ±10 V and 0 V to 20 V, external reference3	3
Offset Error		-10		10	mV	0 V to 20 V, ±10 V ranges, external reference3	4
Offset Error		-6		6	mV	All ranges except ±5 V, ±10 V, and 0 V to 20 V; internal reference	4
Offset Error TC, unipolar ranges		-5		5	µV/°C	Unipolar ranges, external reference3 and internal reference	4
Offset Error TC, bipolar ranges		-15		15	µV/°C	Bipolar ranges, external reference3 and internal reference	4
Gain Error		-0.1		0.1	% FSR	External reference3	4
Gain Error		-0.15		0.15	% FSR	Internal reference	4
Gain Error TC		-1.5		1.5	ppm FSR/°C	External reference3 and internal reference	4
Total Unadjusted Error (TUE)	TUE	-0.1		0.1	% FSR	External reference3	4
Total Unadjusted Error (TUE)	TUE	-0.15		0.15	% FSR	Internal reference	4
Reference Input Current	IREF	-2		2	µA		4
Reference Range (external)	VREF	2		3	V		4
Reference Input Voltage tolerance	VREF	-1		1	%	2.5 V for specified performance	4
Internal Reference Output Voltage tolerance	VREFOUT	-3		3	mV	At ambient temperature; nominal 2.5 V	4
Voltage Reference TC			2	5	ppm/°C		4
Output Voltage Range	VOUT	-10		10	V	VDD/VSS = ±11 V, ±10 V output range	4
Output Voltage Range with 5% overrange	VOUT	-10.5		10.5	V	VDD/VSS = ±11 V, ±10 V output range with 5% overrange	4
Headroom			0.5	1	V	RLOAD = 1 kΩ for all ranges except 0 V to16 V and 0 V to 20 V ranges (RLOAD = 2 kΩ)	4
Output Voltage TC	VOUT	-3		3	ppm FSR/°C	±10 V range, external reference	4
Logic Input Leakage Current	IIN	-1		1	µA	SDI, SCLK, SYNC	4
Logic Input Leakage Current, LDAC/CLEAR/RESET held high	IIN	-1		1	µA	LDAC, CLEAR, RESET pins held high	4
Logic Input Leakage Current, LDAC/CLEAR/RESET held low	IIN	-55			µA	LDAC, CLEAR, RESET pins held low	4
Logic Output Voltage Low	VOL			0.4	V	DVCC = 1.7 V to 5.5 V, sinking 200 µA	5
Positive Analog Supply	VDD	4.75		30	V		5
Negative Analog Supply	VSS	-16.5		0	V		5
Digital Supply	DVCC	1.7		5.5	V		5
Positive Supply Current	IDD		5.1	6.5	mA	Outputs unloaded, external reference	5
Negative Supply Current	ISS		1	3	mA	Outputs unloaded	5
DC Power Supply Rejection Ratio				0.1	mV/V	VDD ± 10%, VSS = −15 V	5
Output Voltage Settling Time, 20 V step	tS		9	12.5	µs	20 V step to 1 LSB at 16-bit resolution	6
Output Voltage Settling Time, 10 V step	tS		7.5	8.5	µs	10 V step to 1 LSB at 16-bit resolution	6
VDD to AGND	VDD	-0.3		34	V	to AGND	9
VSS to AGND	VSS	-17		0.3	V	to AGND	9
VDD to VSS		-0.3		34	V		9
DVCC to DGND	DVCC	-0.3		7	V	to DGND	9
Digital Inputs to DGND		-0.3			V	Upper limit DVCC + 0.3 V or 7 V, whichever is less	9
Digital Outputs to DGND		-0.3			V	Upper limit DVCC + 0.3 V or 7 V, whichever is less	9
VREFIN/VREFOUT to DGND	VREFIN/VREFOUT	-0.3		7	V	to DGND	9
Storage Temperature Range	TSTG	-65		150	°C		9
Junction Temperature	TJ			150	°C	TJ MAX	9
Operating Temperature Range (Industrial)	TA	-40		125	°C		9
Thermal Impedance, junction to ambient (16-lead LFCSP)	θJA		75		°C/W	JEDEC 2S2P test board, still air (0 m/sec airflow)	9
Thermal Impedance, junction to case (16-lead LFCSP)	θJC		4.5		°C/W	Measured to exposed paddle, with infinite heat sink on package top surface	9

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		selectable) and updates the DAC output. This pin can be left floating because there is an internal pull-up resistor. EPAD Exposed Pad. The exposed pad must be mechanically connected to the PCB copper	11

CAD (KiCad official)

Symbol: AD5761RACPZ-RL7
Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
3D model files: ad5761racpz-rl7-etched.step / ad5761racpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5761racpz-rl7.step / ad5761racpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (36 pp, sha256 fa7d48d80133ef52, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5761RACPZ-RL7

Verified AD5761RACPZ-RL7

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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