component
ACS714LLCTR-50A-T
Public Made by Adomby adom
Allegro MicroSystems, LLC Current Sensors, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownACS714LLCTR-50A-T
Allegro MicroSystems, LLC · Current Sensors · SOIC-8
ACS714LLCTR-50A-T from Allegro MicroSystems, LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Terminal for the current being sampled; fused internally, with pins 1 and 2 tied together as the positive current input. |
| 2 | IP+ | passive | Terminal for the current being sampled; fused internally, with pins 1 and 2 tied together as the positive current input. |
| 3 | IP- | passive | Terminal for the current being sampled; fused internally, with pins 3 and 4 tied together as the negative current return. |
| 4 | IP- | passive | Terminal for the current being sampled; fused internally, with pins 3 and 4 tied together as the negative current return. |
| 5 | GND | power_in | Signal ground terminal for the device. |
| 6 | FILTER | passive | Terminal for an external capacitor that sets the bandwidth; the datasheet gives CF = 1 nF as the common operating condition, with RF(INT) = 1.7 kΩ typical forming an RC circuit with it. |
| 7 | VIOUT | output | Analog output signal; limited to 3 mA source and 10 mA sink per the absolute maximum ratings. |
| 8 | VCC | power_in | Device power supply terminal; 4.5 V to 5.5 V with 5.0 V typical, and 8 V absolute maximum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-8 |
| Category | Sensors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 4.5 | 5 | 5.5 | V | 5 | |
| Output Resistive Load | RLOAD | 4.7 | kΩ | VIOUT to GND | 5 | ||
| Output Capacitance Load | CLOAD | 10 | nF | VIOUT to GND | 5 | ||
| Supply Current | ICC | 10 | 13 | mA | VCC = 5.0 V, output open | 5 | |
| Symmetry | ESYM | 98 | 100 | 102 | % | Over full range of IP | 5 |
| Optimized Accuracy Range | IP | -50 | 50 | A | Range L: TA = -40°C to 150°C | 9 | |
| Sensitivity | Sens | 37.5 | 42.5 | mV/A | Over full range of IP, TA = -40°C to 150°C | 9 | |
| Electrical Output Voltage | VOE | -40 | 40 | mV | IP = 0 A, TA = 25°C | 9 | |
| Total Output Error | ETOT | -1.5 | 1.5 | % | IP = ±40 A, TA = 25°C | 9 | |
| Total Output Error | ETOT | -6 | 6 | % | IP = ±40 A, TA = -40°C to 150°C | 9 | |
| Supply Voltage | VCC | 8 | V | 3 | |||
| Reverse Supply Voltage | VRCC | -0.1 | V | 3 | |||
| Output Voltage | VIOUT | 8 | V | 3 | |||
| Reverse Output Voltage | VRIOUT | -0.1 | V | 3 | |||
| Output Current Source | IIOUT(Source) | 3 | mA | 3 | |||
| Output Current Sink | IIOUT(Sink) | 10 | mA | 3 | |||
| Overcurrent Transient Tolerance | IP | 100 | A | 1 pulse, 100 ms | 3 | ||
| Nominal Operating Ambient Temperature (Range L) | TA | -40 | 150 | ºC | Range L | 3 | |
| Maximum Junction Temperature | TJ(max) | 165 | ºC | 3 | |||
| Storage Temperature | Tstg | -65 | 170 | ºC | 3 | ||
| Operating Internal Leadframe Temperature (L range) | TA | -40 | 150 | °C | L range | 5 | |
| Junction-to-Lead Thermal Resistance | RθJL | 5 | °C/W | Mounted on the Allegro ASEK 714 evaluation board | 5 | ||
| Junction-to-Ambient Thermal Resistance | RθJA | 23 | °C/W | Mounted on the Allegro 85-0322 evaluation board, includes the power consumed by the board | 5 |
CAD (KiCad official)
- Symbol:
ACS714LLCTR-50A-T - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
acs714llctr-50a-t-etched.step/acs714llctr-50a-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acs714llctr-50a-t.step/acs714llctr-50a-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (19 pp, sha256
3058a1f592f4f7aa, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).