component
AT25QL128A-MHE-T
Public Made by Adomby adom
Adesto Technologies NOR FLASH, UDFN-8-EP(5x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAT25QL128A-MHE-T
Adesto Technologies · NOR FLASH · UDFN-8-EP(5x6)
AT25QL128A-MHE-T from Adesto Technologies, in a UDFN-8-EP(5x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select is active low: driving it low enables the device, and when it is high the device is deselected with serial outputs in high impedance; a falling edge is required after power-up before any instruction. |
| 2 | SO (IO1) | bidirectional | Serial Output shifts data out on the falling edge of SCK and is high-impedance when CS is deasserted; it becomes IO1 in Dual/Quad modes. |
| 3 | WP (IO2) | bidirectional | Write Protect is active low and protects the Status Register together with the BP and SRP bits, but it is unavailable as a WP function when QE is set to 1 because the pin then serves as IO2. |
| 4 | GND | power_in | GND is the ground reference for the VCC supply and should be connected to the system ground. |
| 5 | SI (IO0) | bidirectional | Serial Input latches data and commands on the rising edge of SCK and is ignored when the device is deselected; it becomes IO0 in Dual/Quad modes. |
| 6 | SCK | input | Serial Clock provides the interface timing, with data latched on its rising edge and shifted out on its falling edge, supporting up to 133 MHz. |
| 7 | HOLD (IO3) | bidirectional | HOLD is active low and pauses serial communication without deselecting or resetting the device when CS is asserted and SCK is low, and it is internally pulled high and should be tied to VCC whenever possible. |
| 8 | VCC | power_in | VCC is the single supply for all device functions and operates from 1.7 V to 2.0 V; operation at invalid VCC voltages may produce spurious results. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Adesto Technologies |
| Package | UDFN-8-EP(5x6) |
| Category | Memory |
| Pins | 9 |
CAD (KiCad official)
- Symbol:
AT25QL128A-MHE-T - Footprint:
Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm - 3D model: UDFN-8-EP(5x6) (KiCad packages3D, STEP)
- 3D model files:
at25ql128a-mhe-t-etched.step/at25ql128a-mhe-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at25ql128a-mhe-t.step/at25ql128a-mhe-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Adesto Technologies datasheet (77 pp, sha256
dfd17c53a54f9712, retrieved 2026-11-02, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).