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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

TPIC6C596DRQ1

Texas Instruments · Shifting Register · SOIC-16

TPIC6C596DRQ1 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC	power_in	Logic supply voltage, recommended 4.5 V to 5.5 V, with an absolute maximum of 7 V referenced to GND.
2	SER IN	input	Serial data input to the 8-bit shift register, which needs at least 15 ns setup and 15 ns hold relative to the rising edge of SRCK.
3	DRAIN0	output	Open-drain low-side power DMOS output rated for 33 V drain-to-source and 100 mA continuous sink current, with 250 mA maximum current limit at TC = 25°C.
4	DRAIN1	output	Open-drain low-side power DMOS output rated for 33 V drain-to-source and 100 mA continuous sink current, with 250 mA maximum current limit at TC = 25°C.
5	DRAIN2	output	Open-drain low-side power DMOS output rated for 33 V drain-to-source and 100 mA continuous sink current, with 250 mA maximum current limit at TC = 25°C.
6	DRAIN3	output	Open-drain low-side power DMOS output rated for 33 V drain-to-source and 100 mA continuous sink current, with 250 mA maximum current limit at TC = 25°C.
7	CLR	input	Active-low shift register clear; when low, all registers in the device are cleared.
8	G	input	Active-low output enable; when held high all output buffers are held low and all drain outputs are off, and when low the storage register is transparent to the output buffers.
9	SER OUT	output	Serial data output clocked out on the falling edge of SRCK, providing additional hold time for cascaded stages.
10	RCK	input	Register clock; on its rising edge the storage register transfers data to the output buffers while CLR is high.
11	DRAIN4	output	Open-drain low-side power DMOS output rated for 33 V drain-to-source and 100 mA continuous sink current, with 250 mA maximum current limit at TC = 25°C.
12	DRAIN5	output	Open-drain low-side power DMOS output rated for 33 V drain-to-source and 100 mA continuous sink current, with 250 mA maximum current limit at TC = 25°C.
13	DRAIN6	output	Open-drain low-side power DMOS output rated for 33 V drain-to-source and 100 mA continuous sink current, with 250 mA maximum current limit at TC = 25°C.
14	DRAIN7	output	Open-drain low-side power DMOS output rated for 33 V drain-to-source and 100 mA continuous sink current, with 250 mA maximum current limit at TC = 25°C.
15	SRCK	input	Shift register clock; data transfers through the shift register on its rising edge.
16	GND	power_in	Power ground; all voltages are referenced to GND and each power DMOS source is internally connected to GND.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Logic ICs
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Logic supply voltage (absolute maximum)	VCC	-0.3		7	V	Voltages referenced to GND	4
Logic input voltage (absolute maximum)	VI	-0.3		7	V		4
Power DMOS drain-to-source voltage (absolute maximum)	VDS	-0.3		33	V		4
Continuous source-to-drain diode anode current				250	mA		4
Pulsed source-to-drain diode anode current				500	mA	Pulse duration ≤ 100 µs, duty cycle ≤ 2%	4
Pulsed drain current, each output	ID			250	mA	All outputs on, TC = 25°C; pulse ≤ 100 µs, duty cycle ≤ 2%	4
Continuous drain current, each output	ID			100	mA	All outputs on, TC = 25°C	4
Peak drain current, single output	IDM			250	mA	TC = 25°C	4
Single-pulse avalanche energy	EAS			30	mJ	See Figure 11	4
Avalanche current	IAS			200	mA	DRAIN supply 15 V, TJS = 25°C, L = 1.5 H	4
Operating case temperature (absolute maximum)	TC	-40		125	°C		4
Operating virtual junction temperature	TJ	-40		150	°C		4
Storage temperature	Tstg	-65		150	°C		4
Logic supply voltage (recommended)	VCC	4.5		5.5	V		4
High-level input voltage	VIH	0.85			V	Printed as 0.85 VCC	4
Low-level input voltage	VIL			0.15	V	Printed as 0.15 VCC	4
Pulsed drain output current				250	mA	TC = 25°C, VCC = 5 V, all outputs on; pulse ≤ 100 µs, duty cycle ≤ 2%	4
Setup time, SER IN high before SRCK↑	tsu	15			ns	See Figure 9	4
Hold time, SER IN high after SRCK↑	th	15			ns	See Figure 9	4
Pulse duration	tw	40			ns	See Figure 9	4
Operating case temperature (recommended)	TC	-40		125	°C		4
Drain-to-source breakdown voltage	V(BR)DSX	33	37		V	ID = 1 mA	5
Source-to-drain diode forward voltage	VSD		0.85	1.2	V	IF = 100 mA	5
High-level output voltage, SER OUT	VOH	4.4	4.49		V	IOH = −20 µA, VCC = 4.5 V	5
High-level output voltage, DRAIN	VOH	4	4.2		V	IOH = −4 mA, VCC = 4.5 V	5
Low-level output voltage, SER OUT	VOL		0.005	0.1	V	IOL = 20 µA, VCC = 4.5 V	5
Low-level output voltage, DRAIN	VOL		0.3	0.5	V	IOL = 4 mA, VCC = 4.5 V	5
High-level input current	IIH			1	µA	VCC = 5.5 V, VI = VCC	5
Low-level input current	IIL			-1	µA	VCC = 5.5 V, VI = 0	5
Logic supply current, all outputs off	ICC		20	200	µA	VCC = 5.5 V, all outputs off	5
Logic supply current, all outputs on	ICC		150	500	µA	VCC = 5.5 V, all outputs on	5
Logic supply current at frequency	ICC(FRQ)		1.2	5	mA	fSRCK = 5 MHz, CL = 30 pF, all outputs off, See Figure 9 and Figure 2	5
OFF-state drain current	IDSX		0.1	0.2	µA	VDS = 30 V, VCC = 5.5 V	5
OFF-state drain current, TC = 125°C	IDSX		0.15	0.3	µA	VCC = 5.5 V, TC = 125°C	5
Static drain-source ON-state resistance	rDS(on)		6.5	9	Ω	ID = 50 mA, VCC = 4.5 V	5
Static drain-source ON-state resistance, TC = 125°C	rDS(on)		9.9	12	Ω	ID = 50 mA, TC = 125°C, VCC = 4.5 V	5
Propagation delay time, low-to-high-level output from G	tPLH			80	ns	VCC = 5 V, TC = 25°C	6
Propagation delay time, high-to-low-level output from G	tPHL			50	ns	CL = 30 pF, ID = 75 mA	6
Rise time, drain output	tr			100	ns	VCC = 5 V, TC = 25°C	6
Fall time, drain output	tf			80	ns	VCC = 5 V, TC = 25°C	6
Propagation delay time, SRCK↓ to SER OUT	tpd			15	ns	CL = 30 pF, ID = 75 mA	6
Serial clock frequency	f(SRCK)			10	MHz	CL = 30 pF, ID = 75 mA	6
Reverse-recovery-current rise time	ta			100	ns	IF = 100 mA, di/dt = 10 A/µs	6
Reverse-recovery time	trr			120	ns	IF = 100 mA, di/dt = 10 A/µs	6
Junction-to-ambient thermal resistance (D, SOIC-16)	RθJA		83.7		°C/W	D (SOIC) 16-pin package	5
Junction-to-case (top) thermal resistance (D, SOIC-16)	RθJC(top)		45.1		°C/W	D (SOIC) 16-pin package	5
Junction-to-board thermal resistance (D, SOIC-16)	RθJB		41.2		°C/W	D (SOIC) 16-pin package	5
Junction-to-top characterization parameter (D, SOIC-16)	ψJT		12.1		°C/W	D (SOIC) 16-pin package	5
Junction-to-board characterization parameter (D, SOIC-16)	ψJB		40.9		°C/W	D (SOIC) 16-pin package	5

CAD (KiCad official)

Symbol: TPIC6C596DRQ1
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: tpic6c596drq1-etched.step / tpic6c596drq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpic6c596drq1.step / tpic6c596drq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (31 pp, sha256 a2fc58849952edbb, retrieved 2026-10-28, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF