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AT91SAM7S256D-AU

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Microchip Tech ATMEL & AVR, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersat91sam7s256d-aufactory-2.0.0extractor-text

Verified AT91SAM7S256D-AU

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier mfr, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AT91SAM7S256D-AU · LQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 775-page datasheet
  • ✓distributor: lcsc C38836, digikey AT91SAM7S256D-AU-ND, mouser 556-AT91SAM7S256D-AU
  • ✓family: LQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-kft74zgk/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.587)
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 74 kB, viewers/symbol.html 42 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ at91sam7s256d-au.kicad_sym✓ at91sam7s256d-au.kicad_mod✓ at91sam7s256d-au.step
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Contents

README

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AT91SAM7S256D-AU

Microchip Tech · ATMEL & AVR · LQFP-64(10x10)

AT91SAM7S256D-AU from Microchip Tech, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ADVREF power_in ADC reference voltage; conversions span 0 V to ADVREF.
2 GND power_in Ground; should be connected as shortly as possible to the system ground plane.
3 AD4 input ADC dedicated analog input channel 4; connect to GND if the voltage regulator and ADC are not used.
4 AD5 input ADC dedicated analog input channel 5; connect to GND if the voltage regulator and ADC are not used.
5 AD6 input ADC dedicated analog input channel 6; connect to GND if the voltage regulator and ADC are not used.
6 AD7 input ADC dedicated analog input channel 7; connect to GND if the voltage regulator and ADC are not used.
7 VDDIN power_in Powers the voltage regulator and the ADC; voltage range 3.0 V to 3.6 V (3.3 V nominal).
8 VDDOUT power_out Output of the 1.8 V voltage regulator; needs 470 pF (or 1 nF) NPO and 2.2 µF (or 3.3 µF) X7R capacitors to GND.
9 PA17/PGMD5/AD0 bidirectional PIO line PA17 multiplexed with programming data PGMD5 and ADC input AD0 (pulled-up input at reset).
10 PA18/PGMD6/AD1 bidirectional PIO line PA18 multiplexed with programming data PGMD6 and ADC input AD1 (pulled-up input at reset).
11 PA21/PGMD9 bidirectional PIO line PA21 multiplexed with fast flash programming data PGMD9.
12 VDDCORE power_in Core logic supply, 1.65 V to 1.95 V (1.8 V typical); required for the device including embedded Flash to operate.
13 PA19/PGMD7/AD2 bidirectional PIO line PA19 multiplexed with programming data PGMD7 and ADC input AD2 (pulled-up input at reset).
14 PA22/PGMD10 bidirectional PIO line PA22 multiplexed with fast flash programming data PGMD10.
15 PA23/PGMD11 bidirectional PIO line PA23 multiplexed with fast flash programming data PGMD11.
16 PA20/PGMD8/AD3 bidirectional PIO line PA20 multiplexed with programming data PGMD8 and ADC input AD3 (pulled-up input at reset).
17 GND power_in Ground; should be connected as shortly as possible to the system ground plane.
18 VDDIO power_in Powers the I/O lines and USB transceivers; 3.0 V to 3.6 V (3.3 V nominal) or 1.65 V to 1.95 V (1.8 V nominal), and USB transceivers are unusable below 3.0 V.
19 PA16/PGMD4 bidirectional PIO line PA16 multiplexed with fast flash programming data PGMD4.
20 PA15/PGMD3 bidirectional PIO line PA15 multiplexed with fast flash programming data PGMD3.
21 PA14/PGMD2 bidirectional PIO line PA14 multiplexed with fast flash programming data PGMD2.
22 PA13/PGMD1 bidirectional PIO line PA13 multiplexed with fast flash programming data PGMD1.
23 PA24/PGMD12 bidirectional PIO line PA24 multiplexed with fast flash programming data PGMD12.
24 VDDCORE power_in Core logic supply, 1.65 V to 1.95 V (1.8 V typical); required for the device including embedded Flash to operate.
25 PA25/PGMD13 bidirectional PIO line PA25 multiplexed with fast flash programming data PGMD13.
26 PA26/PGMD14 bidirectional PIO line PA26 multiplexed with fast flash programming data PGMD14.
27 PA12/PGMD0 bidirectional PIO line PA12 multiplexed with fast flash programming data PGMD0.
28 PA11/PGMM3 bidirectional PIO line PA11 multiplexed with programming mode input PGMM3.
29 PA10/PGMM2 bidirectional PIO line PA10 multiplexed with programming mode input PGMM2.
30 PA9/PGMM1 bidirectional PIO line PA9 multiplexed with programming mode input PGMM1.
31 PA8/PGMM0 bidirectional PIO line PA8 multiplexed with programming mode input PGMM0.
32 PA7/PGMNVALID bidirectional PIO line PA7 multiplexed with PGMNVALID, the programming data direction output (low active).
33 TDI input JTAG/ICE test data input.
34 PA6/PGMNOE bidirectional PIO line PA6 multiplexed with PGMNOE, the programming read input (low active).
35 PA5/PGMRDY bidirectional PIO line PA5 multiplexed with PGMRDY, the programming ready output (high active).
36 PA4/PGMNCMD bidirectional PIO line PA4 multiplexed with PGMNCMD, the programming command input (low active).
37 PA27/PGMD15 bidirectional PIO line PA27 multiplexed with fast flash programming data PGMD15.
38 PA28 bidirectional PIO line PA28 with no alternate function listed in Table 4-1.
39 NRST bidirectional Microcontroller reset, active low, configured as input/output.
40 TST input Test mode select; must be tied low for normal operating conditions, other values are reserved for manufacturing test.
41 PA29 bidirectional PIO line PA29 with no alternate function listed in Table 4-1.
42 PA30 bidirectional PIO line PA30 with no alternate function listed in Table 4-1.
43 PA3 bidirectional PIO line PA3 with no alternate function listed in Table 4-1.
44 PA2/PGMEN2 bidirectional PIO line PA2 multiplexed with PGMEN2, a programming enabling input.
45 VDDIO power_in Powers the I/O lines and USB transceivers; 3.0 V to 3.6 V (3.3 V nominal) or 1.65 V to 1.95 V (1.8 V nominal).
46 GND power_in Ground; should be connected as shortly as possible to the system ground plane.
47 PA1/PGMEN1 bidirectional PIO line PA1 multiplexed with PGMEN1, a programming enabling input.
48 PA0/PGMEN0 bidirectional PIO line PA0 multiplexed with PGMEN0, a programming enabling input.
49 TDO output JTAG/ICE test data output.
50 JTAGSEL input JTAG selection; low selects EmbeddedICE mode, high enables IEEE 1149.1 boundary scan, and a chip reset is required after changing it.
51 TMS input JTAG/ICE test mode select input.
52 PA31 bidirectional PIO line PA31 with no alternate function listed in Table 4-1.
53 TCK input JTAG/ICE test clock input.
54 VDDCORE power_in Core logic supply, 1.65 V to 1.95 V (1.8 V typical); required for the device including embedded Flash to operate.
55 ERASE input External hardware ERASE request; the only way to reset the security bit, which erases the full memory plane and clears lock and GPNVM bits.
56 DDM bidirectional USB device port data line connected to the on-chip USB 2.0 full-speed transceiver.
57 DDP bidirectional USB device port data line connected to the on-chip USB 2.0 full-speed transceiver.
58 VDDIO power_in Powers the I/O lines and USB transceivers; 3.0 V to 3.6 V (3.3 V nominal) or 1.65 V to 1.95 V (1.8 V nominal).
59 VDDFLASH power_in Powers part of the Flash and is required for correct Flash operation; 3.0 V to 3.6 V (3.3 V nominal).
60 GND power_in Ground; should be connected as shortly as possible to the system ground plane.
61 XOUT output Main oscillator output to the crystal.
62 XIN/PGMCK input Main oscillator input, also used as PGMCK, the programming clock input.
63 PLLRC passive PLL connection shown in the block diagram; no electrical limits stated in the extracted text.
64 VDDPLL power_in Powers the oscillator and the PLL; can be connected directly to VDDOUT.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature (Industrial) -40 85 °C 557
Storage Temperature -60 150 °C 557
Voltage on Input Pins with Respect to Ground -0.3 5.5 V 557
Maximum Operating Voltage (VDDCORE and VDDPLL) 2 V 557
Total DC Output Current on all I/O lines 150 mA 64-lead LQFP/QFN package 557
DC Supply Core VDDCORE 1.65 1.95 V 558
DC Supply PLL VDDPLL 1.65 1.95 V 558
DC Supply I/Os VDDIO 3 3.6 V 3.3V range 558
DC Supply I/Os VDDIO 1.65 1.95 V 1.8V range 558
DC Supply Flash VDDFLASH 3 3.6 V 558
Supply Voltage (1.8V regulator input) VDDIN 3 3.3 3.6 V 559
Supply Core Slope TSLOPE 6 V/ms During startup 559
Input Low-level Voltage VIL -0.3 0.8 V VVDDIO from 3.0V to 3.6V 558
Input Low-level Voltage VIL -0.3 0.45 V VVDDIO from 1.65V to 1.95V 558
Input High-level Voltage VIH 2 5.5 V VVDDIO from 3.0V to 3.6V 558
Input High-level Voltage VIH 5.5 V VVDDIO from 1.65V to 1.95V 558
Output Low-level Voltage VOL 0.4 V IO = 8 mA, VVDDIO from 3.0V to 3.6V 558
Output Low-level Voltage VOL 0.1 V IO = 0.3 mA, (CMOS) VVDDIO from 3.0V to 3.6V 558
Output Low-level Voltage VOL 0.2 V IO = 1.5 mA, VVDDIO from 1.65V to 1.95V 558
Input Leakage Current (PA0-PA3) ILEAK 40 400 nA PA0-PA3, pull-up resistors disabled (Typ: TA = 25°C, Max: TA = 85°C) 558
Input Leakage Current (other PIOs) ILEAK 20 200 nA Other PIOs, pull-up resistors disabled (Typ: TA = 25°C, Max: TA = 85°C) 558
Input Pull-up Current (PA17-PA20) IPULLUP 10 20.6 60 µA PA17-PA20, VVDDIO from 3.0V to 3.6V, PAx connected to ground 558
Input Pull-up Current (PA17-PA20) IPULLUP 2.46 5.15 11.5 µA PA17-PA20, VVDDIO from 1.65V to 1.95V, PAx connected to ground 558
Input Pull-up Current (other PIOs and NRST) IPULLUP 143 321 600 µA Other PIOs and NRST, VVDDIO from 3.0V to 3.6V, PAx connected to ground 558
Input Pull-up Current (other PIOs and NRST) IPULLUP 25 75 100 µA Other PIOs and NRST, VVDDIO from 1.65V to 1.95V, PAx connected to ground 558
Input Pull-down Current (TST, ERASE, JTAGSEL) IPULLDOWN 135 295 550 µA VVDDIO from 3.0V to 3.6V, pins connected to VVDDIO 558
Input Pull-down Current (TST, ERASE, JTAGSEL) IPULLDOWN 30 67 130 µA VVDDIO from 1.65V to 1.95V, pins connected to VVDDIO 558
Input Capacitance CIN 13.9 pF 48 or 64 LQFP Package 558
Output Current (PA0-PA3) IO 16 mA VVDDIO from 3.0V to 3.6V 559
Output Current (PA0-PA3) IO 3 mA VVDDIO from 1.65V to 1.95V 559
Output Current (PA17-PA20) IO 2 mA VVDDIO from 3.0V to 3.6V 559
Output Current (PA17-PA20) IO 0.5 mA VVDDIO from 1.65V to 1.95V 559
Output Current (other PIOs) IO 8 mA VVDDIO from 3.0V to 3.6V 559
Output Current (other PIOs) IO 1.5 mA VVDDIO from 1.65V to 1.95V 559
Static Current (SAM7S256/128) ISC 4 20 µA On VVDDCORE = 1.85V, MCK = 500Hz, TA = 25°C; all inputs driven at 1 µA; flash in standby; all peripherals off 559
Static Current (SAM7S256/128) ISC 35 150 µA On VVDDCORE = 1.85V, MCK = 500Hz, TA = 85°C; all inputs driven at 1 µA; flash in standby; all peripherals off 559
Power-up delay (flash) TPU 45 µS SAM7S512/256/128 560
Flash Standby Current @25°C (VDDCORE) ISB 5 µA @25°C, onto VDDCORE = 1.8V 560
Flash Standby Current @25°C (VDDFLASH) ISB 10 µA @25°C, onto VDDFLASH = 3.3V 560
Flash Standby Current @85°C (VDDCORE) ISB 10 µA @85°C, onto VDDCORE = 1.8V 560
Flash Standby Current @85°C (VDDFLASH) ISB 120 µA @85°C, onto VDDFLASH = 3.3V 560
Flash Active Current Random Read @30MHz (VDDCORE) ICC 3 mA Random read @ 30MHz, onto VDDCORE = 1.8V 560
Flash Active Current Random Read @30MHz (VDDFLASH) ICC 0.8 mA Random read @ 30MHz, onto VDDFLASH = 3.3V 560
Flash Active Current Write (VDDCORE) ICC 400 µA Write, onto VDDCORE = 1.8V 560
Flash Active Current Write (VDDFLASH) ICC 5.5 mA Write (one bank for SAM7S512), onto VDDFLASH = 3.3V 560
Output Voltage (1.8V regulator) VVDDOUT 1.81 1.85 1.89 V IO = 20 mA 559
Current Consumption (regulator, after startup) IVDDIN 90 µA After startup, no load 559
Current Consumption (regulator, idle mode) IVDDIN 25 µA After startup, Idle mode, no load 559
Maximum DC Output Current (regulator) IO 100 mA VDDIN = 3.3V 559
Brownout Threshold Level (falling edge) VBOT- 1.65 1.68 1.71 V Falling edge 560
Brownout Hysteresis VHYST 50 65 mV VHYST = VBOT+ - VBOT- 560
Brownout Detector Current Consumption (BOD on) IDD 12 18 µA BOD on (GPNVM0 bit active) 560
Brownout Detector Current Consumption (BOD off) IDD 1 µA BOD off (GPNVM0 bit inactive) 560
RC Oscillator Frequency 1/(tCPRC) 22 32 42 kHz VDDPLL = 1.65V 567
Crystal Oscillator Frequency 1/(tCPMAIN) 3 16 20 MHz 568
PLL Output Frequency (field 00) FOUT 80 160 MHz Field out of CKGR_PLL is 00, SAM7S512/256/128 570
PLL Output Frequency (field 10) FOUT 150 180 MHz Field out of CKGR_PLL is 10, SAM7S512/256/128 570
Master Clock Frequency 1/(tCPMCK) 55 MHz 570

CAD (KiCad official)

  • Symbol: AT91SAM7S256D-AU
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: at91sam7s256d-au-etched.step / at91sam7s256d-au-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at91sam7s256d-au.step / at91sam7s256d-au.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (775 pp, sha256 c65dcff3a27c6c04, retrieved 2026-11-13, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF