component
TPS65981ABIRTQR
Public Made by Adomby adom
Texas Instruments Power Distribution Switches, QFN-56-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS65981ABIRTQR
Texas Instruments · Power Distribution Switches · QFN-56-EP(8x8)
TPS65981ABIRTQR from Texas Instruments, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO8 | bidirectional | General-purpose digital I/O 8; float if configured as push-pull output, otherwise ground with a 1-MΩ resistor when unused. |
| 2 | DEBUG1 | bidirectional | General-purpose digital I/O 15; ground with a 1-MΩ resistor when unused. |
| 3 | SS | output | Soft start; tie to capacitance CSS to ground (driven low at POR). |
| 4 | USB_RP_P | bidirectional | System-side USB2.0 high-speed connection to the port multiplexer; ground with 1-kΩ to 5-MΩ resistance when unused. |
| 5 | USB_RP_N | bidirectional | System-side USB2.0 high-speed connection to the port multiplexer; ground with 1-kΩ to 5-MΩ resistance when unused. |
| 6 | C_USB_TP | bidirectional | Port-side top USB D+ connection to the port multiplexer. |
| 7 | C_USB_TN | bidirectional | Port-side top USB D- connection to the port multiplexer. |
| 8 | C_USB_BP | bidirectional | Port-side bottom USB D+ connection to the port multiplexer. |
| 9 | C_USB_BN | bidirectional | Port-side bottom USB D- connection to the port multiplexer. |
| 10 | C_SBU1 | bidirectional | Port-side sideband-use connection of the port multiplexer. |
| 11 | C_SBU2 | bidirectional | Port-side sideband-use connection of the port multiplexer. |
| 12 | RPD_G1 | passive | Tie to C_CC1 when configured to receive power in dead-battery or no-power condition, otherwise tie to GND. |
| 13 | C_CC1 | bidirectional | Output to Type-C CC or VCONN pin; filter noise with capacitance CC_CC1 to GND. |
| 14 | PP_CABLE | power_in | 5-V supply for C_CC pins; bypass with CPP_CABLE to GND when not tied to PP_5V0, tie to PP_5V0 when unused. |
| 15 | C_CC2 | bidirectional | Output to Type-C CC or VCONN pin; filter noise with capacitance CC_CC2 to GND. |
| 16 | RPD_G2 | passive | Tie to C_CC2 when configured to receive power in dead-battery or no-power condition, otherwise tie to GND. |
| 17 | VBUS | power_in | 5-V output from PP_5V0 and input or output from PP_HV up to 20 V; bypass with CVBUS to GND. |
| 18 | VBUS | power_in | 5-V output from PP_5V0 and input or output from PP_HV up to 20 V; bypass with CVBUS to GND. |
| 19 | GPIO3 | bidirectional | General-purpose digital I/O 3; float if configured as push-pull output, otherwise ground with a 1-MΩ resistor when unused. |
| 20 | GPIO6 | bidirectional | General-purpose digital I/O 6; float if configured as push-pull output, otherwise ground with a 1-MΩ resistor when unused. |
| 21 | RESETZ | bidirectional | General-purpose digital I/O 9; active-low reset output when VIN_3V3 is low (driven low on start-up); float when unused. |
| 22 | BUSPOWERZ | bidirectional | General-purpose digital I/O 10 sampled by ADC at boot; tie to LDO_3V3 through 100 kΩ to disable PP_HV and PP_EXT paths during dead-battery or no-battery boot. |
| 23 | GPIO5 | bidirectional | General-purpose digital I/O 5; can be an HPD receiver; tie high or low through 1 kΩ when used as a configuration input, otherwise ground with 1 MΩ when unused. |
| 24 | MRESET | bidirectional | General-purpose digital I/O 11 that forces RESETZ to assert (by default when pulled high); ground with 1 MΩ when unused. |
| 25 | GPIO2 | bidirectional | General-purpose digital I/O 2; float if configured as push-pull output, otherwise ground with a 1-MΩ resistor when unused. |
| 26 | GPIO4 | bidirectional | General-purpose digital I/O 4 configurable as HPD transistor, HPD receiver, or both for DisplayPort; ground with 1 MΩ when unused. |
| 27 | PP_5V0 | power_in | 5-V supply for VBUS; bypass with CPP_5V0 to GND, tie to GND when unused. |
| 28 | PP_5V0 | power_in | 5-V supply for VBUS; bypass with CPP_5V0 to GND, tie to GND when unused. |
| 29 | SENSEN | input | Sense input for the external high-voltage power path current-sense resistance; short to VBUS when unused. |
| 30 | SENSEP | input | Positive sense input for the external high-voltage power path current-sense resistance; short to VBUS when unused. |
| 31 | HV_GATE1 | output | External NFET gate control for the high-voltage power path (POR: shorted to SENSEP); float when unused. |
| 32 | HV_GATE2 | output | External NFET gate control for the high-voltage power path (POR: shorted to VBUS); float when unused. |
| 33 | PP_HV | power_in | HV supply for VBUS; bypass with CPP_HV to GND, tie to GND when unused. |
| 34 | PP_HV | power_in | HV supply for VBUS; bypass with CPP_HV to GND, tie to GND when unused. |
| 35 | SPI_POCI | input | SPI serial controller input from peripheral; tie to LDO_3V3 through a 3.3-kΩ resistor. |
| 36 | SPI_PICO | output | SPI serial controller output to peripheral; connect directly to SPI flash IC. |
| 37 | SPI_CLK | output | SPI serial clock; connect directly to SPI flash IC. |
| 38 | GPIO7 | bidirectional | General-purpose digital I/O 7; float if configured as push-pull output, otherwise ground with a 1-MΩ resistor when unused. |
| 39 | SPI_CSZ | output | SPI chip select; tie to LDO_3V3 through a 3.3-kΩ resistor. |
| 40 | LDO_1V8D | power_out | Output of the 1.8-V LDO for core digital circuits; bypass with CLDO_1V8D to GND. |
| 41 | GPIO0 | bidirectional | General-purpose digital I/O 0; float if configured as push-pull output, otherwise ground with a 1-MΩ resistor when unused. |
| 42 | VDDIO | power_in | VDD for I/O, optionally powering reconfigurable I/Os instead of LDO_3V3; tie to LDO_3V3 when not used, otherwise bypass with CVDDIO to GND. |
| 43 | I2C_IRQZ | output | I2C port interrupt, active low; implement externally as open-drain with a pull-up, float when unused. |
| 44 | DEBUG_CTL2 | bidirectional | General-purpose digital I/O 17; pin state at power-up sets bit 5 of the I2C address. |
| 45 | DEBUG_CTL1 | bidirectional | General-purpose digital I/O 16; pin state at power-up sets bit 4 of the I2C address. |
| 46 | I2C_SDA | bidirectional | I2C port serial data, open-drain; tie to LDO_3V3 or VDDIO through a 10-kΩ resistor whether used or unused. |
| 47 | I2C_SCL | bidirectional | I2C port serial clock, open-drain; tie to LDO_3V3 or VDDIO through a 10-kΩ resistor whether used or unused. |
| 48 | LDO_BMC | power_out | Output of the USB-PD BMC transceiver output level LDO; bypass with CLDO_BMC to GND. |
| 49 | SWD_DATA | bidirectional | SWD serial data with resistive pull-high at POR; float when unused. |
| 50 | SWD_CLK | input | SWD serial clock with resistive pull-high at POR; float when unused. |
| 51 | LDO_3V3 | power_out | Output of the VBUS to 3.3-V LDO or connected to VIN_3V3 by a switch; main internal supply rail, powers external flash; bypass with CLDO_3V3 to GND. |
| 52 | R_OSC | passive | External resistance setting oscillator accuracy; connect to GND through RR_OSC. |
| 53 | VIN_3V3 | power_in | Supply for core circuitry and I/O; bypass with CVIN_3V3 to GND. |
| 54 | AUX_P | bidirectional | System-side DisplayPort connection to the port multiplexer; ground with 1-kΩ to 5-MΩ resistance when unused. |
| 55 | AUX_N | bidirectional | System-side DisplayPort connection to the port multiplexer; ground with 1-kΩ to 5-MΩ resistance when unused. |
| 56 | LDO_1V8A | power_out | Output of the 1.8-V LDO for core analog circuits; bypass with CLDO_1V8A to GND. |
| 57 | GND | power_in | Ground (exposed thermal pad); connect directly to the ground plane per the Layout Guidelines. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-56-EP(8x8) |
| Category | Power Supply Chip |
| Pins | 57 |
CAD (KiCad official)
- Symbol:
TPS65981ABIRTQR - Footprint:
Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm - 3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
- 3D model files:
tps65981abirtqr-etched.step/tps65981abirtqr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65981abirtqr.step/tps65981abirtqr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (99 pp, sha256
32d5d9c3514f4aa3, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).