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TLV9030L1DCKR

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Texas Instruments Integrated Circuits (ICs), 6-TSSOP, SC-88, SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentintegrated circuits (ics)tlv9030l1dckrfactory-2.0.0extractor-text

Verified TLV9030L1DCKR

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 6 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TLV9030L1DCKR · 6-TSSOP, SC-88, SOT-363 · 6 pins
  • ✓copper: 6 copper pads, none touching another net
  • ✓datasheet: all 6 pin names found in the 40-page datasheet
  • •distributor (warn): no ['lcsc'] number
  • ✓family: Texas_Instruments_TLV9030
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-d7k8djb4/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 6 pins = 6 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 6 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tlv9030l1dckr.kicad_sym✓ tlv9030l1dckr.kicad_mod✓ tlv9030l1dckr.step
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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TLV9030L1DCKR

Texas Instruments · Integrated Circuits (ICs) · 6-TSSOP, SC-88, SOT-363

TLV9030L1DCKR from Texas Instruments, in a 6-TSSOP, SC-88, SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). The symbol is generated from that pin table and the footprint is an Adom_Gen land derived from the manufacturer drawing; the 3D model is generated to fit it.

Pinout

Pin Name Type Function
1 IN+ input Non-inverting (+) input of the comparator, specified for rail-to-rail input operation with fault tolerance up to 6V.
2 V- power_in Negative supply voltage; the supply span VS = (V+) - (V-) is specified from 1.65V to 5.5V.
3 IN- input Inverting (-) input of the comparator, specified for rail-to-rail input operation with fault tolerance up to 6V.
4 OUT output Comparator output, open-drain on the TLV902xL and push-pull on the TLV903xL, with latching behavior set by the L1 or L2 option.
5 CLR input Clear input that resets the output latch; the table specifies a pulse high above 1.2V to clear the output.
6 V+ power_in Positive supply voltage; the supply span VS = (V+) - (V-) is specified from 1.65V to 5.5V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package 6-TSSOP, SC-88, SOT-363
Category Integrated Circuits (ICs)
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VS 1.65 5.5 V 5
Input voltage range (IN+, IN-, CLR) from (V-) -0.2 5.5 V 5
Output voltage range, open drain output, from (V-) 0 5.5 V 5
Ambient temperature TA -40 125 °C 5
Supply voltage VS -0.3 6 V 5
Input pins (IN+, IN-, CLR) from (V-) -0.3 6 V 5
Current into input pins (IN+, IN-, CLR) -10 10 mA 5
Output (OUT) from (V-) -0.3 6 V 5
Junction temperature TJ 150 °C 5
Storage temperature Tstg -65 150 °C 5
Electrostatic discharge, human-body model (HBM) V(ESD) -2000 2000 V Per ANSI/ESDA/JEDEC JS-001 5
Electrostatic discharge, charged-device model (CDM) V(ESD) -1000 1000 V Per ANSI/ESDA/JEDEC JS-002 5
Input threshold voltage VT -1.75 1.75 mV VS = 1.8V and 5V 7
Input threshold voltage VT -2.25 2.25 mV VS = 1.8V and 5V, TA = -40°C to +125°C 7
Input threshold voltage drift dVT/dT -0.5 0.5 µV/°C VS = 1.8V and 5V, TA = -40°C to +125°C 7
Quiescent current per comparator IQ 22 30 µA VS = 1.8V and 5V, No Load, Output Low 7
Quiescent current per comparator IQ 42 µA VS = 1.8V and 5V, No Load, Output Low, TA = -40°C to +125°C 7
Power-supply rejection ratio (push-pull) PSRR 75 95 dB VS = 1.8V to 5V, TA = -40°C to +125°C (push-pull only) 7
Power-supply rejection ratio (open drain) PSRR 80 95 dB VS = 1.8V to 5V, TA = -40°C to +125°C (open drain only) 7
Common-mode rejection ratio CMRR 60 70 dB VS = 5V, (V-), 0.2V < VCM < (V+) + 0.2V, TA = -40°C to +125°C 7
Common-mode rejection ratio CMRR 50 60 dB VS = 1.8V, (V-), 0.2V < VCM < (V+) + 0.2V, TA = -40°C to +125°C 7
Voltage swing from (V-) VOL 75 125 mV ISINK = 4mA, TA = 25°C 7
Voltage swing from (V-) VOL 175 mV ISINK = 4mA, TA = -40°C to +125°C 7
Voltage swing from (V+) (push-pull only) VOH 75 125 mV ISOURCE = 4mA, TA = 25°C (push-pull only) 7
Voltage swing from (V+) (push-pull only) VOH 175 mV ISOURCE = 4mA, TA = -40°C to +125°C (push-pull only) 7
Short-circuit current, sinking ISC 75 85 mA VS = 5V, Sinking 7
Short-circuit current, sourcing (push-pull only) ISC 75 85 mA VS = 5V, Sourcing (push-pull only) 7
Power-on reset voltage (positive) VPOR 1.25 V 7
Input bias current IB 5 pA VCM = VS/2 7
Input offset current IOS 1 pA VCM = VS/2 7
Input capacitance, differential CID 2 pF VCM = VS/2 7
Input capacitance, common mode CIC 3 pF VCM = VS/2 7
Voltage input high threshold of CLR VIH_CLR 1.2 V 7
Voltage input low threshold of CLR VIL_CLR 0.6 V 7
Open-drain output leakage current ILKG 100 pA VPULLUP = (V+), TA = 25°C 7
Propagation delay time, high-to-low (open-drain only) TPD-HL 110 ns VID = -100mV, CLR = 0V, RP = 2.5KΩ 8
Propagation delay time, low-to-high (push-pull only) TPD-LH 125 ns VID = +100mV, CLR = 0V 8
Clear fall to latch reset propagation delay time TPD-CLR-F 25 70 ns CLR = 1.8V to 5V 8
Minimum clear hold pulse time CLR_Min 10 ns CLR = 1.8V to 5V 8
5V output fall time, 80% to 20% TFALL 3 ns VID = -100mV 8
5V output rise time, 20% to 80% (push-pull only) TRISE 3 ns VID = +100mV, push-pull only 8
Power on time PON 35 µs 8
Junction-to-ambient thermal resistance RqJA 210.5 °C/W DCK (SC-70) package 6
Junction-to-case (top) thermal resistance RqJC(top) 143.9 °C/W DCK (SC-70) package 6
Junction-to-board thermal resistance RqJB 64.7 °C/W DCK (SC-70) package 6
Junction-to-top characterization parameter yJT 46.1 °C/W DCK (SC-70) package 6
Junction-to-board characterization parameter yJB 64.5 °C/W DCK (SC-70) package 6

CAD (Adom-generated)

  • Symbol: TLV9030L1DCKR
  • Footprint: Adom_Gen:Texas_Instruments_TLV9030
  • 3D model: generated to fit the land (STEP)
  • 3D model files: tlv9030l1dckr-etched.step / tlv9030l1dckr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv9030l1dckr.step / tlv9030l1dckr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (40 pp, sha256 a8706fdf8ff72411, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: symbol generated from the datasheet pin table; footprint an Adom_Gen land derived from the manufacturer drawing. 3D model generated to fit that land.

Datasheet PDF