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CY8C22545-24AXI

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), TQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercy8c22545-24axifactory-2.0.0extractor-text

Verified CY8C22545-24AXI

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 44 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY8C22545-24AXI · TQFP-44(10x10) · 44 pins
  • ✓copper: 44 copper pads, none touching another net
  • ✓datasheet: all 44 pin names found in the 40-page datasheet
  • ✓distributor: lcsc C2944679, digikey CY8C22545-24AXI-ND, mouser 727-CY8C22545-24AXI
  • ✓family: TQFP-44_10x10mm_P0.8mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-srfyf544/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 44 pins = 44 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 44 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy8c22545-24axi.kicad_sym✓ cy8c22545-24axi.kicad_mod✓ cy8c22545-24axi.step
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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CY8C22545-24AXI

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-44(10x10)

CY8C22545-24AXI from Cypress Semicon, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2[5] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) that serves as the optional ADC external Vref and the analog mux left (ML) input.
2 P2[3] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux left (ML) input.
3 P2[1] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux left (ML) input.
4 Vdd power_in Supply voltage; the device operates from 3.0 V to 5.25 V.
5 P4[5] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux left (ML) input.
6 P4[3] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux left (ML) input.
7 P4[1] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux left (ML) input.
8 Vss power_in Ground connection; all VSS pins should be brought out to one common GND plane (Note 7).
9 P3[7] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux left (ML) input.
10 P3[5] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux left (ML) input.
11 P3[3] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux left (ML) input.
12 P3[1] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux left (ML) input.
13 P1[7] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) that serves as the I2C serial clock (SCL) and analog mux left (ML) input.
14 P1[5] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) that serves as the I2C serial data (SDA) and analog mux left (ML) input.
15 P1[3] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux left (ML) input.
16 P1[1] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) that doubles as the crystal input (XTALin), I2C SCL, ISSP SCLK, and analog mux left (ML) input.
17 Vss power_in Ground connection; all VSS pins should be brought out to one common GND plane (Note 7).
18 P1[0] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) that doubles as the crystal output (XTALout), I2C SDA, ISSP SDATA, and analog mux right (MR) input.
19 P1[2] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
20 P1[4] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) that serves as the optional external clock input (EXTCLK) and analog mux right (MR) input.
21 P1[6] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
22 P3[0] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
23 P3[2] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
24 P3[4] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
25 P3[6] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
26 XRES input Active high external reset pin with internal pull-down.
27 P4[0] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
28 P4[2] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
29 P4[4] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
30 Vss power_in Ground connection; all VSS pins should be brought out to one common GND plane (Note 7).
31 P2[0] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
32 P2[2] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
33 P2[4] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
34 P2[6] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input and to comparator column 1.
35 P0[0] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
36 P0[2] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
37 P0[4] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
38 P0[6] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux right (MR) input.
39 Vdd power_in Supply voltage; the device operates from 3.0 V to 5.25 V.
40 P0[7] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) that serves as the integration capacitor for the MR analog input and routed to the analog mux right (MR) input.
41 P0[5] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) that serves as the integration capacitor for the ML analog input and routed to the analog mux left (ML) input.
42 P0[3] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux left (ML) input.
43 P0[1] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux left (ML) input.
44 P2[7] bidirectional GPIO port pin capable of digital I/O (25 mA sink, 10 mA source) and routed to the analog mux left (ML) input and to comparator column 0.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package TQFP-44(10x10)
Category Single Chip Microcomputer/Microcontroller
Pins 44

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature TSTG -55 100 °C 14
Bake temperature TBAKETEMP 125 °C 14
Bake time TBAKETIME 72 Hours 14
Ambient temperature with power applied TA -40 85 °C Power applied 14
Supply voltage on Vdd relative to Vss Vdd -0.5 6 V Relative to Vss 14
Maximum current into any port pin IMIO -25 50 mA 14
Electrostatic discharge voltage ESD 2000 V Human Body Model ESD 14
Latch up current LU 200 mA 14
Ambient temperature TA -40 85 °C 14
Junction temperature TJ -40 100 °C 14
Supply voltage Vdd 3 5.25 V 15
Supply current IDD 7 12 mA Vdd = 5.0 V, 25°C, CPU = 3 MHz, 48 MHz disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz 15
Supply current IDD3 4 7 mA Vdd = 3.3 V, TA = 25 °C, CPU = 3 MHz, 48 MHz disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz 15
Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT ISB 3 6.5 µA Internal slow speed oscillator, Vdd = 3.3 V, -40 °C <= TA <= 55 °C 15
Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature ISBH 4 25 µA Internal slow speed oscillator, Vdd = 3.3 V, 55 °C < TA <= 85 °C 15
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal ISBXTL 4 7.5 µA Properly loaded, 1 W max, 32.768 kHz crystal, Vdd = 3.3 V, -40 °C <= TA <= 55 °C 15
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature ISBXTLH 5 26 µA Properly loaded, 1 W max, 32.768 kHz crystal, Vdd = 3.3 V, 55 °C < TA <= 85 °C 15
Reference Voltage (Bandgap) VREF 1.275 1.3 1.325 V Trimmed for appropriate Vdd 15
Pull-up resistor RPU 4 5.6 8 kΩ 16
Pull-down resistor RPD 4 5.6 8 kΩ 16
Low output level VOL 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25 V 16
High level source current IOH 10 mA VOH = Vdd - 1.0 V 16
Low level sink current IOL 25 mA VOL = 0.75 V 16
Input Low level VIL 0.8 V Vdd = 3.0 to 5.25 16
Input High level VIH 2.1 V Vdd = 3.0 to 5.25 16
Capacitive load on pins as input CIN 3.5 10 pF Package and pin dependent. Temp = 25 °C 16
Capacitive load on pins as output COUT 3.5 10 pF Package and pin dependent. Temp = 25 °C 16
VDD for programming and erase VDDP 4.5 5 5.5 V 20
Low VDD for verify VDDLV 3 3.1 3.2 V 20
High VDD for verify VDDHV 5.1 5.2 5.3 V 20
Supply voltage for flash write operation VDDIWRITE 3 5.25 V Device executing internal flash writes 20
Supply Current during Programming or Verify IDDP 5 25 mA 20
Input Low Voltage during Programming or Verify VILP 0.8 V 20
Input High Voltage during Programming or Verify VIHP 2.2 V 20
Flash Endurance (per block) FlashENPB 50000 Erase/write cycles per block 20
Flash Data Retention FlashDR 10 Years 20
Internal Main Oscillator Frequency for 24 MHz FIMO24 22.8 24 25.2 MHz Trimmed for 5 V or 3.3 V operation using factory trim values. SLIMO mode = 0 < 85 21
Internal Main Oscillator Frequency for 6 MHz FIMO6 5.5 6 6.5 MHz Trimmed for 5 V or 3.3 V operation using factory trim values. SLIMO mode = 0 < 85 21
CPU Frequency (5 V Nominal) FCPU1 0.089 24 MHz 24 MHz only for SLIMO mode = 0 21
CPU Frequency (3.3 V Nominal) FCPU2 0.089 12 MHz SLIMO mode = 0 21
Digital PSoC Block Frequency (5 V Nominal) FBLK5 0 48 MHz 21
Digital PSoC Block Frequency (3.3 V Nominal) FBLK33 0 24 MHz 21
Internal Low Speed Oscillator Frequency F32K1 15 32 85 kHz 21
Untrimmed Internal Low Speed Oscillator Frequency F32KU 5 100 kHz ILO not adjusted with factory trim values until after CPU starts running 21
External Reset Pulse Width TXRES 10 µs Minimum pulse width required to achieve complete device reset 21
24 MHz Duty Cycle DC24M 40 50 60 % 21
Internal Low Speed Oscillator Duty Cycle DCILO 20 50 80 % 21
Maximum frequency of signal on row input or row output FMAX 12.3 MHz 21
Power supply slew rate SRPOWERUP 250 V/ms Vdd slew rate during power up 21
Time from end of POR to CPU executing code TPOWERUP 100 ms 21
GPIO operating frequency FGPIO 12 MHz Normal Strong Mode 22
Rise time, normal strong mode TRiseF 3 18 ns Cload = 50 pF; Vdd = 4.5 to 5.25 V, 10% to 90% 22
Fall time, normal strong mode TFallF 2 18 ns Cload = 50 pF; Vdd = 4.5 to 5.25 V, 10% to 90% 22
Rise time, slow strong mode TRiseS 7 27 ns Cload = 50 pF; Vdd = 3 to 5.25 V, 10% to 90% 22
Fall time, slow strong mode TFallS 7 22 ns Cload = 50 pF; Vdd = 3 to 5.25 V, 10% to 90% 22
LPC response time TRLPC 50 µs 50 mV overdrive comparator reference set within VREFLPC 22
Data Out Delay from Falling Edge of SCLK TDSCLK 55 ns 3.6 < Vdd; at 30 pF Load 25
Flash Block Erase + Flash Block Write Time (hot) TPROGRAM_HOT 100 ms 25
Flash Block Erase + Flash Block Write Time (cold) TPROGRAM_COLD 200 ms 25
Thermal impedance, junction to ambient (typical) JA 61 °C/W 44-pin TQFP; TJ = TA + POWER x JA 28

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC The emulator consists of a base unit that connects to the PC 6

CAD (KiCad official)

  • Symbol: CY8C22545-24AXI
  • Footprint: Package_QFP:TQFP-44_10x10mm_P0.8mm
  • 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
  • 3D model files: cy8c22545-24axi-etched.step / cy8c22545-24axi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c22545-24axi.step / cy8c22545-24axi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (40 pp, sha256 d84b5190da05c378, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF