component
MC74AC163DR2G
Public Made by Adomby adom
onsemi Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC74AC163DR2G
onsemi · Counters, Dividers · SOIC-16
MC74AC163DR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SR | input | Synchronous Reset input (MR on the '161 variant); a LOW overrides counting and parallel loading and lets all outputs go LOW on the next rising CP edge. |
| 2 | CP | input | Clock pulse input; all Q outputs change only on the LOW-to-HIGH transition of CP. |
| 3 | P0 | input | Parallel data input 0, loaded into flip-flop Q0 on the rising CP edge when PE is LOW. |
| 4 | P1 | input | Parallel data input 1, loaded into flip-flop Q1 on the rising CP edge when PE is LOW. |
| 5 | P2 | input | Parallel data input 2, loaded into flip-flop Q2 on the rising CP edge when PE is LOW. |
| 6 | P3 | input | Parallel data input 3, loaded into flip-flop Q3 on the rising CP edge when PE is LOW. |
| 7 | CEP | input | Count Enable Parallel input; counting requires CEP and CET both HIGH, and a LOW on CEP inhibits counting. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | PE | input | Parallel Enable input; a LOW overrides counting and loads the Pn data into the flip-flops on the next rising CP edge. |
| 10 | CET | input | Count Enable Trickle input; counting requires CET HIGH, and a LOW inhibits counting and holds the TC output low. |
| 11 | Q3 | output | Flip-flop output Q3 (binary MSB), capable of sourcing and sinking 24 mA. |
| 12 | Q2 | output | Flip-flop output Q2, capable of sourcing and sinking 24 mA. |
| 13 | Q1 | output | Flip-flop output Q1, capable of sourcing and sinking 24 mA. |
| 14 | Q0 | output | Flip-flop output Q0 (binary LSB), capable of sourcing and sinking 24 mA. |
| 15 | TC | output | Terminal Count output, HIGH when CET is HIGH and the counter is in state 15; it is subject to decoding spikes and is not recommended as a clock or asynchronous reset. |
| 16 | VCC | power_in | Supply voltage; 2.0 to 6.0 V for the AC family, 4.5 to 5.5 V for the ACT family, per the recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (′AC devices) | VCC | 2 | 5 | 6 | V | ′AC devices | 4 |
| DC Input Voltage, Output Voltage (Ref. to GND) | VIN, VOUT | 0 | V | Referenced to GND; maximum printed as VCC | 4 | ||
| Input Rise and Fall Time (′AC except Schmitt inputs) | tr, tf | 150 | ns/V | VCC @ 3.0 V | 4 | ||
| Input Rise and Fall Time (′AC except Schmitt inputs) | tr, tf | 40 | ns/V | VCC @ 4.5 V | 4 | ||
| Input Rise and Fall Time (′AC except Schmitt inputs) | tr, tf | 25 | ns/V | VCC @ 5.5 V | 4 | ||
| Operating Ambient Temperature Range | TA | -40 | 25 | 85 | °C | 4 | |
| Output Current − High | IOH | -24 | mA | 4 | |||
| Output Current − Low | IOL | 24 | mA | 4 | |||
| DC Supply Voltage | VCC | -0.5 | 7 | V | 3 | ||
| DC Input Voltage | VI | -0.5 | V | Upper limit printed as VCC + 0.5 V (symbols garbled in text) | 3 | ||
| DC Output Voltage (Note 1) | VO | -0.5 | V | Upper limit printed as VCC + 0.5 V (symbols garbled in text) | 3 | ||
| DC Input Diode Current | IIK | 20 | mA | 3 | |||
| DC Output Diode Current | IOK | 50 | mA | 3 | |||
| DC Output Sink/Source Current | IO | 50 | mA | 3 | |||
| DC Supply Current per Output Pin | ICC | 50 | mA | 3 | |||
| DC Ground Current per Output Pin | IGND | 50 | mA | 3 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 3 | ||
| Junction temperature under Bias | TJ | 150 | °C | 3 | |||
| Thermal Resistance | JA | 69.1 | °C/W | Per JESD51-7 (Note 2) | 3 | ||
| Power Dissipation in Still Air | PD | 500 | mW | At 65°C; derate to 300 mW at 85°C (Note 3) | 3 | ||
| ESD Withstand Voltage, Human Body Model | VESD | 2000 | V | HBM, printed > 2000 (Note 4) | 3 | ||
| Minimum High Level Input Voltage | VIH | 2.1 | 1.5 | V | VCC 3.0 V; VOUT = 0.1 V or VCC − 0.1 V; TA −40°C to +85°C | 4 | |
| Minimum High Level Input Voltage | VIH | 3.15 | 2.25 | V | VCC 4.5 V; VOUT = 0.1 V or VCC − 0.1 V; TA −40°C to +85°C | 4 | |
| Minimum High Level Input Voltage | VIH | 3.85 | 2.75 | V | VCC 5.5 V; VOUT = 0.1 V or VCC − 0.1 V; TA −40°C to +85°C | 4 | |
| Maximum Low Level Input Voltage | VIL | 1.5 | 0.9 | V | VCC 3.0 V; VOUT = 0.1 V or VCC − 0.1 V; TA −40°C to +85°C | 4 | |
| Maximum Low Level Input Voltage | VIL | 2.25 | 1.35 | V | VCC 4.5 V; VOUT = 0.1 V or VCC − 0.1 V; TA −40°C to +85°C | 4 | |
| Maximum Low Level Input Voltage | VIL | 2.75 | 1.65 | V | VCC 5.5 V; VOUT = 0.1 V or VCC − 0.1 V; TA −40°C to +85°C | 4 | |
| Minimum High Level Output Voltage | VOH | 2.9 | 2.99 | V | VCC 3.0 V; IOUT = −50 µA; TA −40°C to +85°C | 4 | |
| Minimum High Level Output Voltage | VOH | 4.4 | 4.49 | V | VCC 4.5 V; IOUT = −50 µA; TA −40°C to +85°C | 4 | |
| Minimum High Level Output Voltage | VOH | 5.4 | 5.49 | V | VCC 5.5 V; IOUT = −50 µA; TA −40°C to +85°C | 4 | |
| Minimum High Level Output Voltage | VOH | 2.46 | V | VCC 3.0 V; VIN = VIL or VIH; IOH = −12 mA; TA −40°C to +85°C | 4 | ||
| Minimum High Level Output Voltage | VOH | 3.76 | V | VCC 4.5 V; VIN = VIL or VIH; IOH = −24 mA; TA −40°C to +85°C | 4 | ||
| Minimum High Level Output Voltage | VOH | 4.76 | V | VCC 5.5 V; VIN = VIL or VIH; IOH = −24 mA; TA −40°C to +85°C | 4 | ||
| Maximum Low Level Output Voltage | VOL | 0.002 | 0.1 | V | VCC 3.0 V; IOUT = 50 µA; TA −40°C to +85°C | 4 | |
| Maximum Low Level Output Voltage | VOL | 0.001 | 0.1 | V | VCC 4.5 V; IOUT = 50 µA; TA −40°C to +85°C | 4 | |
| Maximum Low Level Output Voltage | VOL | 0.44 | V | VCC 3.0 V; VIN = VIL or VIH; IOL = 12 mA; TA −40°C to +85°C | 4 | ||
| Maximum Input Leakage Current | IIN | -1 | 1 | µA | VCC 5.5 V; VI = VCC, GND; TA −40°C to +85°C | 4 | |
| Minimum Dynamic Output Current | IOLD | 75 | mA | VCC 5.5 V; VOLD = 1.65 V Max | 4 | ||
| Minimum Dynamic Output Current | IOHD | -75 | mA | VCC 5.5 V; VOHD = 3.85 V Min | 4 | ||
| Maximum Quiescent Supply Current | ICC | 80 | µA | VCC 5.5 V; VIN = VCC or GND; TA −40°C to +85°C | 4 | ||
| Maximum Count Frequency | fmax | 95 | 140 | MHz | VCC 5.0 V ±0.5 V; CL = 50 pF; TA −40°C to +85°C | 5 | |
| Propagation Delay CP to Qn (PE HIGH or LOW) | tPLH | 1 | 5.5 | 9.5 | ns | VCC 5.0 V ±0.5 V; CL = 50 pF; TA −40°C to +85°C | 5 |
| Propagation Delay CP to Qn (PE HIGH or LOW) | tPHL | 1.5 | 6 | 10 | ns | VCC 5.0 V ±0.5 V; CL = 50 pF; TA −40°C to +85°C | 5 |
| Propagation Delay CP to TC | tPLH | 1.5 | 7 | 11.5 | ns | VCC 5.0 V ±0.5 V; CL = 50 pF; TA −40°C to +85°C | 5 |
| Propagation Delay CP to TC | tPHL | 2 | 8 | 11.5 | ns | VCC 5.0 V ±0.5 V; CL = 50 pF; TA −40°C to +85°C | 5 |
| Propagation Delay CET to TC | tPLH | 1 | 5.5 | 7.5 | ns | VCC 5.0 V ±0.5 V; CL = 50 pF; TA −40°C to +85°C | 5 |
| Propagation Delay CET to TC | tPHL | 1.5 | 6 | 9.5 | ns | VCC 5.0 V ±0.5 V; CL = 50 pF; TA −40°C to +85°C | 5 |
| Setup Time Pn to CP (HIGH or LOW) | ts | 10.5 | 4 | ns | VCC 5.0 V ±0.5 V; TA −40°C to +85°C | 7 | |
| Hold Time Pn to CP (HIGH or LOW) | th | 0 | -5 | ns | VCC 5.0 V ±0.5 V; TA −40°C to +85°C | 7 | |
| Setup Time SR to CP (HIGH or LOW) | ts | 11 | 4 | ns | VCC 5.0 V ±0.5 V; TA −40°C to +85°C | 7 | |
| Hold Time SR to CP (HIGH or LOW) | th | 0 | -5.5 | ns | VCC 5.0 V ±0.5 V; TA −40°C to +85°C | 7 | |
| Setup Time PE to CP (HIGH or LOW) | ts | 8.5 | 4 | ns | VCC 5.0 V ±0.5 V; TA −40°C to +85°C | 7 | |
| Hold Time PE to CP (HIGH or LOW) | th | 0 | -5 | ns | VCC 5.0 V ±0.5 V; TA −40°C to +85°C | 7 | |
| Setup Time CEP or CET to CP (HIGH or LOW) | ts | 5 | 2.5 | ns | VCC 5.0 V ±0.5 V; TA −40°C to +85°C | 7 | |
| Hold Time CEP or CET to CP (HIGH or LOW) | th | 0.5 | -3 | ns | VCC 5.0 V ±0.5 V; TA −40°C to +85°C | 7 | |
| Clock Pulse Width (Load) HIGH or LOW | tw | 3 | 2 | ns | VCC 5.0 V ±0.5 V; TA −40°C to +85°C | 7 | |
| Clock Pulse Width (Count) HIGH or LOW | tw | 3.5 | 2 | ns | VCC 5.0 V ±0.5 V; TA −40°C to +85°C | 7 |
CAD (KiCad official)
- Symbol:
MC74AC163DR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mc74ac163dr2g-etched.step/mc74ac163dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74ac163dr2g.step/mc74ac163dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (13 pp, sha256
5bacfa2bf29bd96b, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).