component
74ALVC573PW
Public Made by Adomby adom
Nexperia Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74ALVC573PW
Nexperia · Latches · TSSOP-20
74ALVC573PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Output enable input (active LOW); a HIGH level forces the Qn outputs to the high-impedance OFF-state without affecting the latch contents. |
| 2 | D0 | input | Data input for latch 0; while LE is HIGH the latch is transparent and Q0 follows D0, and D0 must be stable a set-up time before the HIGH-to-LOW transition of LE. |
| 3 | D1 | input | Data input for latch 1; while LE is HIGH the latch is transparent and Q1 follows D1, and D1 must be stable a set-up time before the HIGH-to-LOW transition of LE. |
| 4 | D2 | input | Data input for latch 2; while LE is HIGH the latch is transparent and Q2 follows D2, and D2 must be stable a set-up time before the HIGH-to-LOW transition of LE. |
| 5 | D3 | input | Data input for latch 3; while LE is HIGH the latch is transparent and Q3 follows D3, and D3 must be stable a set-up time before the HIGH-to-LOW transition of LE. |
| 6 | D4 | input | Data input for latch 4; while LE is HIGH the latch is transparent and Q4 follows D4, and D4 must be stable a set-up time before the HIGH-to-LOW transition of LE. |
| 7 | D5 | input | Data input for latch 5; while LE is HIGH the latch is transparent and Q5 follows D5, and D5 must be stable a set-up time before the HIGH-to-LOW transition of LE. |
| 8 | D6 | input | Data input for latch 6; while LE is HIGH the latch is transparent and Q6 follows D6, and D6 must be stable a set-up time before the HIGH-to-LOW transition of LE. |
| 9 | D7 | input | Data input for latch 7; while LE is HIGH the latch is transparent and Q7 follows D7, and D7 must be stable a set-up time before the HIGH-to-LOW transition of LE. |
| 10 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 11 | LE | input | Latch enable input (active HIGH); when LE goes LOW the latches store the information present at the Dn inputs. |
| 12 | Q7 | tri_state | 3-state latch output 7; goes high-impedance when OE is HIGH. |
| 13 | Q6 | tri_state | 3-state latch output 6; goes high-impedance when OE is HIGH. |
| 14 | Q5 | tri_state | 3-state latch output 5; goes high-impedance when OE is HIGH. |
| 15 | Q4 | tri_state | 3-state latch output 4; goes high-impedance when OE is HIGH. |
| 16 | Q3 | tri_state | 3-state latch output 3; goes high-impedance when OE is HIGH. |
| 17 | Q2 | tri_state | 3-state latch output 2; goes high-impedance when OE is HIGH. |
| 18 | Q1 | tri_state | 3-state latch output 1; goes high-impedance when OE is HIGH. |
| 19 | Q0 | tri_state | 3-state latch output 0; goes high-impedance when OE is HIGH. |
| 20 | VCC | power_in | Supply voltage; recommended operating range is 1.65 V to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 4.6 | V | 5 | ||
| input voltage | VI | -0.5 | 4.6 | V | 5 | ||
| output voltage, output HIGH or LOW state (max printed as VCC + 0.5 V) | VO | -0.5 | V | 5 | |||
| output voltage, output 3-state | VO | -0.5 | 4.6 | V | 5 | ||
| output voltage, power-down mode | VO | -0.5 | 4.6 | V | VCC = 0 V | 5 | |
| input clamping current | IIK | -50 | mA | VI < 0 V | 5 | ||
| output clamping current | IOK | -50 | 50 | mA | VO > VCC or VO < 0 V | 5 | |
| output current | IO | -50 | 50 | mA | VO = 0 V to VCC | 5 | |
| supply current | ICC | 100 | mA | 5 | |||
| ground current | IGND | -100 | mA | 5 | |||
| storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 5 | ||
| supply voltage | VCC | 1.65 | 3.6 | V | 6 | ||
| input voltage | VI | 0 | 3.6 | V | 6 | ||
| output voltage, output HIGH or LOW state (max printed as VCC) | VO | 0 | V | 6 | |||
| output voltage, output 3-state | VO | 0 | 3.6 | V | 6 | ||
| output voltage, power-down mode | VO | 0 | 3.6 | V | VCC = 0 V | 6 | |
| ambient temperature in free air | Tamb | -40 | 125 | °C | 6 | ||
| input transition rise and fall rate | Δt/ΔV | 20 | ns/V | VCC = 1.65 V to 2.7 V | 6 | ||
| input transition rise and fall rate | Δt/ΔV | 10 | ns/V | VCC = 2.7 V to 3.6 V | 6 | ||
| HIGH-level input voltage | VIH | 1.7 | V | Tamb -40 °C to +125 °C; VCC = 2.3 V to 2.7 V | 6 | ||
| HIGH-level input voltage | VIH | 2 | V | Tamb -40 °C to +125 °C; VCC = 2.7 V to 3.6 V | 6 | ||
| LOW-level input voltage | VIL | 0.7 | V | Tamb -40 °C to +125 °C; VCC = 2.3 V to 2.7 V | 6 | ||
| LOW-level input voltage | VIL | 0.8 | V | Tamb -40 °C to +125 °C; VCC = 2.7 V to 3.6 V | 6 | ||
| HIGH-level output voltage | VOH | 1.25 | 1.51 | V | Tamb -40 °C to +125 °C; IO = -6 mA; VCC = 1.65 V | 6 | |
| HIGH-level output voltage | VOH | 1.8 | 2.1 | V | Tamb -40 °C to +125 °C; IO = -12 mA; VCC = 2.3 V | 6 | |
| HIGH-level output voltage | VOH | 1.7 | 2.01 | V | Tamb -40 °C to +125 °C; IO = -18 mA; VCC = 2.3 V | 6 | |
| HIGH-level output voltage | VOH | 2.2 | 2.53 | V | Tamb -40 °C to +125 °C; IO = -12 mA; VCC = 2.7 V | 6 | |
| HIGH-level output voltage | VOH | 2.4 | 2.76 | V | Tamb -40 °C to +125 °C; IO = -18 mA; VCC = 3.0 V | 6 | |
| HIGH-level output voltage | VOH | 2.2 | 2.68 | V | Tamb -40 °C to +125 °C; IO = -24 mA; VCC = 3.0 V | 6 | |
| LOW-level output voltage | VOL | 0.2 | V | Tamb -40 °C to +125 °C; IO = 100 μA; VCC = 1.65 V to 3.6 V | 6 | ||
| LOW-level output voltage | VOL | 0.11 | 0.3 | V | Tamb -40 °C to +125 °C; IO = 6 mA; VCC = 1.65 V | 6 | |
| LOW-level output voltage | VOL | 0.17 | 0.4 | V | Tamb -40 °C to +125 °C; IO = 12 mA; VCC = 2.3 V | 6 | |
| LOW-level output voltage | VOL | 0.25 | 0.6 | V | Tamb -40 °C to +125 °C; IO = 18 mA; VCC = 2.3 V | 6 | |
| LOW-level output voltage | VOL | 0.16 | 0.4 | V | Tamb -40 °C to +125 °C; IO = 12 mA; VCC = 2.7 V | 6 | |
| LOW-level output voltage | VOL | 0.23 | 0.45 | V | Tamb -40 °C to +125 °C; IO = 18 mA; VCC = 3.0 V | 6 | |
| LOW-level output voltage | VOL | 0.3 | 0.55 | V | Tamb -40 °C to +125 °C; IO = 24 mA; VCC = 3.0 V | 6 | |
| input leakage current | II | -20 | 0.1 | 20 | μA | Tamb -40 °C to +125 °C; VCC = 3.6 V; VI = 3.6 V or GND | 6 |
| OFF-state output current | IOZ | -80 | 0.1 | 80 | μA | Tamb -40 °C to +125 °C; VI = VIH or VIL; VCC = 1.65 V to 3.6 V; VO = 3.6 V or GND | 7 |
| power-off leakage supply current | IOFF | -80 | 0.1 | 80 | μA | Tamb -40 °C to +125 °C; VCC = 0 V; VI or VO = 0 V to 3.6 V | 7 |
| supply current | ICC | 0.2 | 80 | μA | Tamb -40 °C to +125 °C; VCC = 3.6 V; VI = VCC or GND; IO = 0 A | 7 | |
| additional supply current per input pin | ΔICC | 5 | 750 | μA | Tamb -40 °C to +125 °C; per input pin; VCC = 3.0 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A | 7 | |
| propagation delay Dn to Qn | tpd | 1 | 2.5 | 6.2 | ns | Tamb -40 °C to +125 °C; Dn to Qn; see Fig. 6; VCC = 1.65 V to 1.95 V | 7 |
| propagation delay Dn to Qn | tpd | 1 | 2 | 4 | ns | Tamb -40 °C to +125 °C; Dn to Qn; see Fig. 6; VCC = 2.3 V to 2.7 V | 7 |
| propagation delay Dn to Qn | tpd | 1 | 2.3 | 4.1 | ns | Tamb -40 °C to +125 °C; Dn to Qn; see Fig. 6; VCC = 2.7 V | 7 |
| propagation delay Dn to Qn | tpd | 1 | 2.2 | 3.8 | ns | Tamb -40 °C to +125 °C; Dn to Qn; see Fig. 6; VCC = 3.0 V to 3.6 V | 7 |
| propagation delay LE to Qn | tpd | 1 | 2.8 | 6.9 | ns | Tamb -40 °C to +125 °C; LE to Qn; see Fig. 7; VCC = 1.65 V to 1.95 V | 7 |
| propagation delay LE to Qn | tpd | 1 | 2.1 | 4.4 | ns | Tamb -40 °C to +125 °C; LE to Qn; see Fig. 7; VCC = 2.3 V to 2.7 V | 7 |
| propagation delay LE to Qn | tpd | 1 | 2.4 | 4.3 | ns | Tamb -40 °C to +125 °C; LE to Qn; see Fig. 7; VCC = 2.7 V | 7 |
| propagation delay LE to Qn | tpd | 1 | 2.3 | 3.8 | ns | Tamb -40 °C to +125 °C; LE to Qn; see Fig. 7; VCC = 3.0 V to 3.6 V | 7 |
| enable time OE to Qn | ten | 1.5 | 3 | 7.4 | ns | Tamb -40 °C to +125 °C; OE to Qn; see Fig. 8; VCC = 1.65 V to 1.95 V | 7 |
| enable time OE to Qn | ten | 1 | 2.4 | 5.2 | ns | Tamb -40 °C to +125 °C; OE to Qn; see Fig. 8; VCC = 2.3 V to 2.7 V | 7 |
| enable time OE to Qn | ten | 1.5 | 3 | 5.3 | ns | Tamb -40 °C to +125 °C; OE to Qn; see Fig. 8; VCC = 2.7 V | 7 |
| enable time OE to Qn | ten | 1 | 2.3 | 4.6 | ns | Tamb -40 °C to +125 °C; OE to Qn; see Fig. 8; VCC = 3.0 V to 3.6 V | 7 |
| disable time OE to Qn | tdis | 1.5 | 3.4 | 8.1 | ns | Tamb -40 °C to +125 °C; OE to Qn; see Fig. 8; VCC = 1.65 V to 1.95 V | 7 |
| disable time OE to Qn | tdis | 1 | 2.2 | 5.1 | ns | Tamb -40 °C to +125 °C; OE to Qn; see Fig. 8; VCC = 2.3 V to 2.7 V | 7 |
| disable time OE to Qn | tdis | 1.5 | 2.8 | 5.1 | ns | Tamb -40 °C to +125 °C; OE to Qn; see Fig. 8; VCC = 2.7 V | 7 |
| disable time OE to Qn | tdis | 1 | 2.7 | 5.1 | ns | Tamb -40 °C to +125 °C; OE to Qn; see Fig. 8; VCC = 3.0 V to 3.6 V | 7 |
| LE pulse width HIGH | tW | 3.8 | ns | Tamb -40 °C to +125 °C; LE pulse width HIGH; see Fig. 7; VCC = 1.65 V to 1.95 V | 7 | ||
| LE pulse width HIGH | tW | 3.3 | ns | Tamb -40 °C to +125 °C; LE pulse width HIGH; see Fig. 7; VCC = 2.3 V to 2.7 V | 7 |
CAD (KiCad official)
- Symbol:
74ALVC573PW - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
74alvc573pw-etched.step/74alvc573pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74alvc573pw.step/74alvc573pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (17 pp, sha256
82f9ddbbee793380, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).