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CD4025BM96
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4025BM96
Texas Instruments · Logic Gates · SOIC-14
CD4025BM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Input A of the first 3-input NOR gate (output J = NOT(A+B+C)); input range -0.5V to VDD+0.5V. |
| 2 | B | input | Input B of the first 3-input NOR gate (output J = NOT(A+B+C)); input range -0.5V to VDD+0.5V. |
| 3 | D | input | Input D of the second 3-input NOR gate (output K = NOT(D+E+F)); input range -0.5V to VDD+0.5V. |
| 4 | E | input | Input E of the second 3-input NOR gate (output K = NOT(D+E+F)); input range -0.5V to VDD+0.5V. |
| 5 | F | input | Input F of the second 3-input NOR gate (output K = NOT(D+E+F)); input range -0.5V to VDD+0.5V. |
| 6 | K | output | Output of the second 3-input NOR gate, K = NOT(D+E+F). |
| 7 | VSS | power_in | Ground (VSS) supply terminal; supply voltages are referenced to it. |
| 8 | C | input | Input C of the first 3-input NOR gate (output J = NOT(A+B+C)); input range -0.5V to VDD+0.5V. |
| 9 | J | output | Output of the first 3-input NOR gate, J = NOT(A+B+C). |
| 10 | L | output | Output of the third 3-input NOR gate, L = NOT(G+H+I). |
| 11 | I | input | Input I of the third 3-input NOR gate (output L = NOT(G+H+I)); input range -0.5V to VDD+0.5V. |
| 12 | H | input | Input H of the third 3-input NOR gate (output L = NOT(G+H+I)); input range -0.5V to VDD+0.5V. |
| 13 | G | input | Input G of the third 3-input NOR gate (output L = NOT(G+H+I)); input range -0.5V to VDD+0.5V. |
| 14 | VDD | power_in | Positive supply voltage, recommended 3V to 18V, absolute maximum -0.5V to +20V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD4025BM96 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
cd4025bm96-etched.step/cd4025bm96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4025bm96.step/cd4025bm96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
29898c1b5c0da39b, retrieved 2026-10-01, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).