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SN74ACT08N

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Texas Instruments Gates, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74ACT08N

Texas Instruments · Gates · PDIP-14

SN74ACT08N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of gate 1; inputs are TTL-voltage compatible and accept voltages up to 5.5 V, and unused inputs must be held at VCC or GND.
2 1B input Input B of gate 1 (Y = A·B); inputs are TTL-voltage compatible and accept voltages up to 5.5 V, and unused inputs must be held at VCC or GND.
3 1Y output Output of gate 1; rated for high-level output current of −24 mA and low-level output current of 24 mA.
4 2A input Input A of gate 2; inputs are TTL-voltage compatible and accept voltages up to 5.5 V, and unused inputs must be held at VCC or GND.
5 2B input Input B of gate 2; inputs are TTL-voltage compatible and accept voltages up to 5.5 V, and unused inputs must be held at VCC or GND.
6 2Y output Output of gate 2; rated for high-level output current of −24 mA and low-level output current of 24 mA.
7 GND power_in Ground pin of the device.
8 3Y output Output of gate 3; rated for high-level output current of −24 mA and low-level output current of 24 mA.
9 3A input Input A of gate 3; inputs are TTL-voltage compatible and accept voltages up to 5.5 V, and unused inputs must be held at VCC or GND.
10 3B input Input B of gate 3; inputs are TTL-voltage compatible and accept voltages up to 5.5 V, and unused inputs must be held at VCC or GND.
11 4Y output Output of gate 4; rated for high-level output current of −24 mA and low-level output current of 24 mA.
12 4A input Input A of gate 4; inputs are TTL-voltage compatible and accept voltages up to 5.5 V, and unused inputs must be held at VCC or GND.
13 4B input Input B of gate 4; inputs are TTL-voltage compatible and accept voltages up to 5.5 V, and unused inputs must be held at VCC or GND.
14 VCC power_in Supply pin; recommended supply range is 4.5 V to 5.5 V (absolute maximum 7 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5.5 V 2
High-level input voltage VIH 2 V 2
Low-level input voltage VIL 0.8 V 2
Input voltage VI 0 V Maximum printed as VCC 2
Output voltage VO 0 V Maximum printed as VCC 2
High-level output current IOH -24 mA 2
Low-level output current IOL 24 mA 2
Input transition rise or fall rate ∆t/∆v 8 ns/V 2
Operating free-air temperature TA -40 85 °C SN74ACT08 2
Supply voltage VCC -0.5 7 V 2
Input voltage range VI -0.5 V Maximum printed as VCC + 0.5 V; see Note 1 2
Output voltage range VO -0.5 V Maximum printed as VCC + 0.5 V; see Note 1 2
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 2
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 2
Continuous output current IO -50 50 mA VO = 0 to VCC 2
Continuous current through VCC or GND ICC -200 200 mA 2
Storage temperature range Tstg -65 150 °C 2
Package thermal impedance, N package θJA 80 °C/W N package; see Note 2 (JESD 51-7) 2
High-level output voltage VOH 4.4 4.49 V IOH = -50 µA; VCC 4.5 V 3
High-level output voltage VOH 5.4 5.49 V IOH = -50 µA; VCC 5.5 V 3
High-level output voltage VOH 3.76 3.86 V IOH = -24 mA; VCC 4.5 V 3
High-level output voltage VOH 4.76 4.86 V IOH = -24 mA; VCC 5.5 V 3
Low-level output voltage VOL 0.001 0.1 V IOL = 50 µA; VCC 4.5 V 3
Low-level output voltage VOL 0.36 0.44 V IOL = 24 mA; VCC 4.5 V 3
Input current II 0.1 1 µA VI = VCC or GND; VCC 5.5 V 3
Supply current ICC 2 20 µA VI = VCC or GND, IO = 0; VCC 5.5 V 3
Supply current increase per input ICC 0.6 1.5 mA One input at 3.4 V, other inputs at GND or VCC; VCC 5.5 V 3
Propagation delay low-to-high tPLH 1 6.5 10 ns A or B to Y; VCC = 5 V ± 0.5 V; see Figure 1 3
Propagation delay high-to-low tPHL 1 6.5 10 ns A or B to Y; VCC = 5 V ± 0.5 V; see Figure 1 3

CAD (KiCad official)

  • Symbol: SN74ACT08N
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74act08n-etched.step / sn74act08n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74act08n.step / sn74act08n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 31184e98349d4df4, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF