component
74HC03D
Public Made by Adomby adom
Nexperia Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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Datasheet
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README
markdown74HC03D
Nexperia · Logic Gates · SOIC-14
74HC03D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input A of NAND gate 1; input voltage must stay between 0 V and VCC, and clamp diodes limit input current to ±20 mA when the input is beyond the rails by 0.5 V. |
| 2 | 1B | input | Data input B of NAND gate 1; input voltage must stay between 0 V and VCC, and clamp diodes limit input current to ±20 mA when the input is beyond the rails by 0.5 V. |
| 3 | 1Y | output | Open-drain output of NAND gate 1 that pulls LOW when both inputs are HIGH and is high-impedance otherwise; output voltage is limited to -0.5 V to +7 V and output current to -25 mA. |
| 4 | 2A | input | Data input A of NAND gate 2; input voltage must stay between 0 V and VCC, and clamp diodes limit input current to ±20 mA when the input is beyond the rails by 0.5 V. |
| 5 | 2B | input | Data input B of NAND gate 2; input voltage must stay between 0 V and VCC, and clamp diodes limit input current to ±20 mA when the input is beyond the rails by 0.5 V. |
| 6 | 2Y | output | Open-drain output of NAND gate 2 that pulls LOW when both inputs are HIGH and is high-impedance otherwise; output voltage is limited to -0.5 V to +7 V and output current to -25 mA. |
| 7 | GND | power_in | Ground reference (0 V) for all voltages in the device. |
| 8 | 3Y | output | Open-drain output of NAND gate 3 that pulls LOW when both inputs are HIGH and is high-impedance otherwise; output voltage is limited to -0.5 V to +7 V and output current to -25 mA. |
| 9 | 3A | input | Data input A of NAND gate 3; input voltage must stay between 0 V and VCC, and clamp diodes limit input current to ±20 mA when the input is beyond the rails by 0.5 V. |
| 10 | 3B | input | Data input B of NAND gate 3; input voltage must stay between 0 V and VCC, and clamp diodes limit input current to ±20 mA when the input is beyond the rails by 0.5 V. |
| 11 | 4Y | output | Open-drain output of NAND gate 4 that pulls LOW when both inputs are HIGH and is high-impedance otherwise; output voltage is limited to -0.5 V to +7 V and output current to -25 mA. |
| 12 | 4A | input | Data input A of NAND gate 4; input voltage must stay between 0 V and VCC, and clamp diodes limit input current to ±20 mA when the input is beyond the rails by 0.5 V. |
| 13 | 4B | input | Data input B of NAND gate 4; input voltage must stay between 0 V and VCC, and clamp diodes limit input current to ±20 mA when the input is beyond the rails by 0.5 V. |
| 14 | VCC | power_in | Supply voltage; 2.0 V to 6.0 V for 74HC03 and 4.5 V to 5.5 V for 74HCT03. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | 2 | 5 | 6 | V | 3 | |
| input voltage | VI | 0 | V | 3 | |||
| output voltage | VO | 0 | V | 3 | |||
| ambient temperature | Tamb | -40 | 25 | 125 | °C | 3 | |
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 3 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 3 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 3 | ||
| supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| output voltage | VO | -0.5 | 7 | V | 3 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 3 | |
| output clamping current | IOK | -20 | mA | VO < -0.5 V | 3 | ||
| output current | IO | -25 | mA | -0.5 V < VO | 3 | ||
| supply current | ICC | 50 | mA | 3 | |||
| ground current | IGND | -50 | mA | 3 | |||
| storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| total power dissipation | Ptot | 500 | mW | 3 | |||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | 25 °C; VCC = 2.0 V | 4 | |
| HIGH-level input voltage | VIH | 1.5 | V | -40 °C to +125 °C; VCC = 2.0 V | 4 | ||
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | 25 °C; VCC = 4.5 V | 4 | |
| HIGH-level input voltage | VIH | 3.15 | V | -40 °C to +125 °C; VCC = 4.5 V | 4 | ||
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | 25 °C; VCC = 6.0 V | 4 | |
| HIGH-level input voltage | VIH | 4.2 | V | -40 °C to +125 °C; VCC = 6.0 V | 4 | ||
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | 25 °C; VCC = 2.0 V | 4 | |
| LOW-level input voltage | VIL | 0.5 | V | -40 °C to +125 °C; VCC = 2.0 V | 4 | ||
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | 25 °C; VCC = 4.5 V | 4 | |
| LOW-level input voltage | VIL | 1.35 | V | -40 °C to +125 °C; VCC = 4.5 V | 4 | ||
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | 25 °C; VCC = 6.0 V | 4 | |
| LOW-level input voltage | VIL | 1.8 | V | -40 °C to +125 °C; VCC = 6.0 V | 4 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; 25 °C | 4 | |
| LOW-level output voltage | VOL | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C | 4 | ||
| LOW-level output voltage | VOL | 0.15 | 0.26 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; 25 °C | 4 | |
| LOW-level output voltage | VOL | 0.4 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 4 | ||
| LOW-level output voltage | VOL | 0.16 | 0.26 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; 25 °C | 4 | |
| input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 4 | |
| OFF-state output current | IOZ | -0.5 | 0.5 | μA | VI = VIL; VCC = 6.0 V; VO = VCC or GND; 25 °C | 4 | |
| OFF-state output current | IOZ | -10 | 10 | μA | VI = VIL; VCC = 6.0 V; VO = VCC or GND; -40 °C to +125 °C | 4 | |
| supply current | ICC | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 4 | ||
| propagation delay | tpd | 28 | 95 | ns | nA, nB to nY; CL = 50 pF; see Fig. 4; VCC = 2.0 V; 25 °C | 5 | |
| propagation delay | tpd | 145 | ns | nA, nB to nY; CL = 50 pF; see Fig. 4; VCC = 2.0 V; -40 °C to +125 °C | 5 | ||
| propagation delay | tpd | 10 | 19 | ns | nA, nB to nY; CL = 50 pF; see Fig. 4; VCC = 4.5 V; 25 °C | 5 | |
| propagation delay | tpd | 29 | ns | nA, nB to nY; CL = 50 pF; see Fig. 4; VCC = 4.5 V; -40 °C to +125 °C | 5 | ||
| propagation delay | tpd | 8 | 16 | ns | nA, nB to nY; CL = 50 pF; see Fig. 4; VCC = 6.0 V; 25 °C | 5 | |
| propagation delay | tpd | 25 | ns | nA, nB to nY; CL = 50 pF; see Fig. 4; VCC = 6.0 V; -40 °C to +125 °C | 5 | ||
| transition time | tt | 19 | 75 | ns | CL = 50 pF; see Fig. 4; VCC = 2.0 V; 25 °C | 5 | |
| transition time | tt | 110 | ns | CL = 50 pF; see Fig. 4; VCC = 2.0 V; -40 °C to +125 °C | 5 | ||
| transition time | tt | 7 | 15 | ns | CL = 50 pF; see Fig. 4; VCC = 4.5 V; 25 °C | 5 | |
| transition time | tt | 22 | ns | CL = 50 pF; see Fig. 4; VCC = 4.5 V; -40 °C to +125 °C | 5 | ||
| transition time | tt | 6 | 13 | ns | CL = 50 pF; see Fig. 4; VCC = 6.0 V; 25 °C | 5 | |
| transition time | tt | 19 | ns | CL = 50 pF; see Fig. 4; VCC = 6.0 V; -40 °C to +125 °C | 5 |
CAD (KiCad official)
- Symbol:
74HC03D - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
74hc03d-etched.step/74hc03d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc03d.step/74hc03d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (11 pp, sha256
0f83483437aa5fc1, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).