A 3-to-8 line decoder/demultiplexer with a built-in address latch, in high-speed CMOS, SOIC-16. Like the 74HC138 it drives one of eight outputs from a 3-bit address, but here the outputs are active-high and a latch-enable pin can freeze the address so the selected output stays put after the address bus moves on. That suits multiplexed-bus systems where the address appears only briefly. Two output-enable inputs gate the whole device and allow cascading. Runs 2-6 V.

Pinout

Pin	Name	Type	Function
1	A0	input	Address select input bit 0 (LSB). Combined with A1 and A2 selects which of eight Y outputs is driven high. Latched by LE; transparent when LE is low, held on the LE low-to-high transition.
2	A1	input	Address select input bit 1. Combined with A0 and A2 selects which of eight Y outputs is driven high. Latched by LE.
3	A2	input	Address select input bit 2 (MSB). Combined with A0 and A1 selects which of eight Y outputs is driven high. Latched by LE.
4	LE	input	Latch Enable, active low. When LE is low the address inputs A0-A2 pass transparently to the decoder; on the low-to-high transition of LE the current address is latched and further changes on A0-A2 are ignored.
5	~{OE1}	input	Output Enable 1, active low. Must be low together with OE0 high to enable the selected Y output. When high, all outputs are forced to their inactive state (LOW for 'HC237/'HCT237).
6	OE0	input	Output Enable 0, active high. Must be high together with /OE1 low to enable the selected Y output. When low, all outputs are forced to their inactive state (LOW for 'HC237/'HCT237).
7	Y7	output	Decoded output 7 (address 111). Driven HIGH when selected and both enables active; otherwise LOW. Fanout 10 LSTTL loads (standard) / 15 LSTTL loads (bus driver).
8	GND	power_in	Ground reference (0 V) for logic and outputs.
9	Y6	output	Decoded output 6 (address 110). Driven HIGH when selected and both enables active; otherwise LOW.
10	Y5	output	Decoded output 5 (address 101). Driven HIGH when selected and both enables active; otherwise LOW.
11	Y4	output	Decoded output 4 (address 100). Driven HIGH when selected and both enables active; otherwise LOW.
12	Y3	output	Decoded output 3 (address 011). Driven HIGH when selected and both enables active; otherwise LOW.
13	Y2	output	Decoded output 2 (address 010). Driven HIGH when selected and both enables active; otherwise LOW.
14	Y1	output	Decoded output 1 (address 001). Driven HIGH when selected and both enables active; otherwise LOW.
15	Y0	output	Decoded output 0 (address 000). Driven HIGH when selected and both enables active; otherwise LOW.
16	VCC	power_in	Positive supply. HC variant: 2 V to 6 V. HCT variant: 4.5 V to 5.5 V. Decouple with a local 0.1 uF ceramic to GND close to the pin.

Key specifications

Parameter	Value
Type	3-to-8 decoder/demux, latched
Address	3-bit (A0-A2), latchable
Outputs	8 active-high (Y0-Y7)
Latch	LE holds the address
Enables	OE0 + /OE1
Logic family	HC (high-speed CMOS)
Supply voltage	2-6 V
Package	SOIC-16

Ordering variants

Same part, different packaging or reel option.

CD74HC237M (SOIC-16, tube)
CD74HC237M96 (SOIC-16, tape & reel)

CAD (KiCad official)

Symbol: 74xx:74HC237
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (27 pp, sha256 564c040df4c1b784, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF