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ADS6443IRGCT

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Texas Instruments Analog To Digital Converters (ADC), QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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ADS6443IRGCT

Texas Instruments · Analog To Digital Converters (ADC) · QFN-64-EP(9x9)

ADS6443IRGCT from Texas Instruments, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DA1_P output Channel A differential LVDS serial data output pair, wire 1 (positive leg) in the 2-wire interface.
2 DA1_M output Channel A differential LVDS serial data output pair, wire 1 (negative leg) in the 2-wire interface.
3 DA0_P output Channel A differential LVDS serial data output pair, wire 0 (positive leg) in the 2-wire interface.
4 DA0_M output Channel A differential LVDS serial data output pair, wire 0 (negative leg) in the 2-wire interface.
5 CAP passive Connect a 2-nF capacitor from this pin to ground.
6 RESET input Serial interface reset input; a high-going pulse initializes the registers in serial mode, and it must be tied permanently high in parallel mode (internal pull-down).
7 LVDD power_in Digital (LVDS buffer) power supply, 3.0 V to 3.6 V with 3.3 V nominal.
8 AGND power_in Analog ground.
9 AVDD power_in Analog power supply, 3.0 V to 3.6 V with 3.3 V nominal.
10 AGND power_in Analog ground.
11 INA_M input Differential analog input, channel A (negative); 2 Vpp differential range with 1.5 V ±0.1 V common mode; tie to VCM if unused, do not float.
12 INA_P input Differential analog input, channel A (positive); 2 Vpp differential range with 1.5 V ±0.1 V common mode; tie to VCM if unused, do not float.
13 AGND power_in Analog ground.
14 INB_M input Differential analog input, channel B (negative); 2 Vpp differential range with 1.5 V ±0.1 V common mode; tie to VCM if unused, do not float.
15 INB_P input Differential analog input, channel B (positive); 2 Vpp differential range with 1.5 V ±0.1 V common mode; tie to VCM if unused, do not float.
16 AGND power_in Analog ground.
17 AVDD power_in Analog power supply, 3.0 V to 3.6 V with 3.3 V nominal.
18 AGND power_in Analog ground.
19 AVDD power_in Analog power supply, 3.0 V to 3.6 V with 3.3 V nominal.
20 NC unconnected Do not connect.
21 CFG4 input Parallel input that selects MSB/LSB first and the data format (Table 11).
22 VCM bidirectional Common-mode voltage output in internal reference mode; reference input in external reference mode, 1.45 V to 1.55 V (1.50 V nominal).
23 AGND power_in Analog ground.
24 CLKP input Differential ADC sampling clock input (ac-coupled); sine clock amplitude 0.4 Vpp to 1.5 Vpp with 35% to 65% duty cycle.
25 CLKM input Differential ADC sampling clock input (ac-coupled); sine clock amplitude 0.4 Vpp to 1.5 Vpp with 35% to 65% duty cycle.
26 AGND power_in Analog ground.
27 AVDD power_in Analog power supply, 3.0 V to 3.6 V with 3.3 V nominal.
28 CFG3 input Reserved pin; tie to ground.
29 CFG2 input Parallel input that selects 14x/16x serialization and the SDR bit clock capture edge (Table 9); tie to ground or AVDD for 14x with DDR bit clock.
30 CFG1 input Parallel input that selects 1-wire/2-wire interface and DDR/SDR bit clock (Table 8); tie to AVDD for 2-wire interface with DDR bit clock.
31 AGND power_in Analog ground.
32 AVDD power_in Analog power supply, 3.0 V to 3.6 V with 3.3 V nominal.
33 AGND power_in Analog ground.
34 INC_P input Differential analog input, channel C (positive); 2 Vpp differential range with 1.5 V ±0.1 V common mode; tie to VCM if unused, do not float.
35 INC_M input Differential analog input, channel C (negative); 2 Vpp differential range with 1.5 V ±0.1 V common mode; tie to VCM if unused, do not float.
36 AGND power_in Analog ground.
37 IND_P input Differential analog input, channel D (positive); 2 Vpp differential range with 1.5 V ±0.1 V common mode; tie to VCM if unused, do not float.
38 IND_M input Differential analog input, channel D (negative); 2 Vpp differential range with 1.5 V ±0.1 V common mode; tie to VCM if unused, do not float.
39 AGND power_in Analog ground.
40 AVDD power_in Analog power supply, 3.0 V to 3.6 V with 3.3 V nominal.
41 PDN input Global power-down control; AVDD powers the device down globally, and 0 selects normal operation.
42 SEN input Serial interface enable when RESET is low; sets coarse gain and internal/external reference when RESET is high (internal pull-up).
43 SDATA input Serial interface data when RESET is low; controls sync, deskew and global power-down when RESET is high (internal pull-down).
44 SCLK input Serial interface clock when RESET is low; controls sync, deskew and global power-down when RESET is high (internal pull-down).
45 DD1_P output Channel D differential LVDS serial data output pair, wire 1 (positive leg) in the 2-wire interface.
46 DD1_M output Channel D differential LVDS serial data output pair, wire 1 (negative leg) in the 2-wire interface.
47 DD0_P output Channel D differential LVDS serial data output pair, wire 0 (positive leg) in the 2-wire interface.
48 DD0_M output Channel D differential LVDS serial data output pair, wire 0 (negative leg) in the 2-wire interface.
49 LVDD power_in Digital (LVDS buffer) power supply, 3.0 V to 3.6 V with 3.3 V nominal.
50 DC1_P output Channel C differential LVDS serial data output pair, wire 1 (positive leg) in the 2-wire interface.
51 DC1_M output Channel C differential LVDS serial data output pair, wire 1 (negative leg) in the 2-wire interface.
52 DC0_P output Channel C differential LVDS serial data output pair, wire 0 (positive leg) in the 2-wire interface.
53 DC0_M output Channel C differential LVDS serial data output pair, wire 0 (negative leg) in the 2-wire interface.
54 LGND power_in Digital ground.
55 FCLKP output Differential LVDS frame clock output pair (positive leg).
56 FCLKM output Differential LVDS frame clock output pair (negative leg).
57 DCLKP output Differential LVDS bit clock output pair (positive leg).
58 DCLKM output Differential LVDS bit clock output pair (negative leg).
59 LGND power_in Digital ground.
60 DB1_P output Channel B differential LVDS serial data output pair, wire 1 (positive leg) in the 2-wire interface.
61 DB1_M output Channel B differential LVDS serial data output pair, wire 1 (negative leg) in the 2-wire interface.
62 DB0_P output Channel B differential LVDS serial data output pair, wire 0 (positive leg) in the 2-wire interface.
63 DB0_M output Channel B differential LVDS serial data output pair, wire 0 (negative leg) in the 2-wire interface.
64 LVDD power_in Digital (LVDS buffer) power supply, 3.0 V to 3.6 V with 3.3 V nominal.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-64-EP(9x9)
Category Data Acquisition
Pins 65

CAD (KiCad official)

  • Symbol: ADS6443IRGCT
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ads6443irgct-etched.step / ads6443irgct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads6443irgct.step / ads6443irgct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (81 pp, sha256 24ebd34353014618, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF