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AD7124-4BRUZ-RL7
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Analog Devices Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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README
markdownAD7124-4BRUZ-RL7
Analog Devices · Analog To Digital Converters (ADC) · TSSOP-24
AD7124-4BRUZ-RL7 from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIN | input | Serial data input to the ADC input shift register; the communications register register-select bits determine which control register the data is transferred to. |
| 2 | SCLK | input | Serial clock input for ADC data transfers, with a Schmitt-triggered input suitable for opto-isolated applications; it may be continuous or non-continuous. |
| 3 | CLK | bidirectional | Clock input/output: the internal 614.4 kHz clock can be made available here, or the internal clock can be disabled and the ADC driven by an external clock. |
| 4 | CS | input | Active-low chip select that selects the ADC; it can be hardwired low for 3-wire operation when SPI diagnostics are unused. |
| 5 | REGCAPD | power_out | Digital LDO regulator output that must be decoupled to DGND with a 0.1 µF capacitor. |
| 6 | IOVDD | power_in | Serial interface supply voltage of 1.65 V to 3.6 V, independent of AVDD. |
| 7 | DGND | power_in | Digital ground reference point. |
| 8 | AIN0/IOUT/VBIAS | passive | Analog input 0 (positive or negative terminal of a differential or pseudo-differential input), alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage, midway between the analog supply rails. |
| 9 | AIN1/IOUT/VBIAS | passive | Analog input 1 (positive or negative terminal of a differential or pseudo-differential input), alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage, midway between the analog supply rails. |
| 10 | AIN2/IOUT/VBIAS/P1 | passive | Analog input 2, alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage, or configured as general-purpose output P1 referenced between AVSS and AVDD. |
| 11 | AIN3/IOUT/VBIAS/P2 | passive | Analog input 3, alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage, or configured as general-purpose output P2 referenced between AVSS and AVDD. |
| 12 | REFIN1(+) | passive | Positive external reference input; the nominal REFIN1(+) − REFIN1(−) is 2.5 V, the device functions with a reference from 0.5 V to AVDD, and REFIN1(+) can be anywhere between AVDD and AVSS + 0.5 V. |
| 13 | REFIN1(−) | passive | Negative external reference input, which can be anywhere between AVSS and AVDD − 0.5 V. |
| 14 | AIN4/IOUT/VBIAS | passive | Analog input 4, alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage midway between the analog supply rails. |
| 15 | AIN5/IOUT/VBIAS | passive | Analog input 5, alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage midway between the analog supply rails. |
| 16 | AIN6/IOUT/VBIAS/REFIN2(+) | passive | Analog input 6, alternatively the IOUT0/IOUT1 excitation current output or VBIAS, and also the positive reference input for REFIN2(±), with the nominal 2.5 V reference functioning from 0.5 V to AVDD. |
| 17 | AIN7/IOUT/VBIAS/REFIN2(−) | passive | Analog input 7, alternatively the IOUT0/IOUT1 excitation current output or VBIAS, and also the negative reference input for REFIN2(±), which can be anywhere between AVSS and AVDD − 0.5 V. |
| 18 | REFOUT | output | Buffered output of the internal 2.5 V voltage reference. |
| 19 | AVSS | power_in | Analog supply ground; AVDD − AVSS must be 2.7 V to 3.6 V in mid or low power mode and 2.9 V to 3.6 V in full power mode, and AVSS may be taken below 0 V (e.g., −1.8 V) for a dual supply. |
| 20 | REGCAPA | power_out | Analog LDO regulator output that must be decoupled to AVSS with a 0.1 µF capacitor. |
| 21 | PSW | passive | Low-side power switch to AVSS, rated for 30 mA continuous current with 10 Ω maximum on-resistance. |
| 22 | AVDD | power_in | Analog supply voltage relative to AVSS, 2.7 V to 3.6 V in mid or low power mode and 2.9 V to 3.6 V in full power mode. |
| 23 | SYNC | input | Synchronization logic input; when low it resets the digital filter, filter control and calibration control logic and holds the modulator in reset, and it also resets RDY high. |
| 24 | DOUT/RDY | output | Serial data output and data-ready output; the pin goes low to indicate conversion completion and, with CS low, data is placed on the SCLK falling edge and is valid on the SCLK rising edge. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-24 |
| Category | Data Acquisition |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| AVDD to AVSS supply, Low Power Mode | 2.7 | 3.6 | V | Low Power Mode | 10 | ||
| AVDD to AVSS supply, Mid Power Mode | 2.7 | 3.6 | V | Mid Power Mode | 10 | ||
| AVDD to AVSS supply, Full Power Mode | 2.9 | 3.6 | V | Full Power Mode | 10 | ||
| IOVDD to GND supply | 1.65 | 3.6 | V | 10 | |||
| AVSS to GND | -1.8 | 0 | V | 10 | |||
| AVDD to AVSS absolute max | -0.3 | 3.96 | V | TA = 25°C | 14 | ||
| IOVDD to DGND absolute max | -0.3 | 3.96 | V | TA = 25°C | 14 | ||
| IOVDD to AVSS absolute max | -0.3 | 5.94 | V | TA = 25°C | 14 | ||
| AVSS to DGND absolute max | -1.98 | 0.3 | V | TA = 25°C | 14 | ||
| Operating temperature range | -40 | 125 | °C | 14 | |||
| Storage temperature range | -65 | 150 | °C | 14 | |||
| Maximum junction temperature | 150 | °C | 14 | ||||
| Absolute input current, buffered, Low Power Mode | -1 | 1 | nA | Gain > 1 or Gain = 1 (Buffered); Low Power Mode | 8 | ||
| Differential input current, buffered, Low Power Mode | -0.2 | 0.2 | nA | Gain > 1 or Gain = 1 (Buffered); Low Power Mode | 8 | ||
| Absolute input current, buffered, Mid Power Mode | -1.2 | 1.2 | nA | Gain > 1 or Gain = 1 (Buffered); Mid Power Mode | 8 | ||
| Differential input current, buffered, Mid Power Mode | -0.4 | 0.4 | nA | Gain > 1 or Gain = 1 (Buffered); Mid Power Mode | 8 | ||
| Absolute input current, buffered, Full Power Mode | -3.3 | 3.3 | nA | Gain > 1 or Gain = 1 (Buffered); Full Power Mode | 8 | ||
| Differential input current, buffered, Full Power Mode | -1.5 | 1.5 | nA | Gain > 1 or Gain = 1 (Buffered); Full Power Mode | 8 | ||
| Absolute input current, unbuffered | -2.65 | 2.65 | µA/V | Gain = 1 (Unbuffered); current varies with input voltage | 8 | ||
| Internal reference initial accuracy | -0.2 | 0.2 | % | TA = 25°C; nominal 2.5 V | 8 | ||
| Internal reference drift, TSSOP | 2 | 10 | ppm/°C | TSSOP package | 8 | ||
| External REFIN voltage | 0.5 | 2.5 | V | REFIN = REFINx(+) − REFINx(−); max printed as AVDD | 8 | ||
| Reference input current, buffered, Low Power Mode | -0.5 | 0.5 | nA | Buffered; Low Power Mode | 8 | ||
| Reference input current, buffered, Mid Power Mode | -1 | 1 | nA | Buffered; Mid Power Mode | 8 | ||
| Reference input current, buffered, Full Power Mode | -3 | 3 | nA | Buffered; Full Power Mode | 8 | ||
| Reference input current, unbuffered | -12 | 12 | µA | Unbuffered | 8 | ||
| Excitation current initial tolerance | -4 | 4 | % | TA = 25°C | 9 | ||
| Excitation current matching | -0.5 | 0.5 | % | Matching between IOUT0 and IOUT1, VOUT = 0 V | 9 | ||
| Excitation current drift matching | 5 | 30 | ppm/°C | 9 | |||
| Temperature sensor accuracy | -0.5 | 0.5 | °C | 9 | |||
| Low-side power switch on resistance | RON | 7 | 10 | Ω | 9 | ||
| Reference detect level | 0.7 | 1 | V | REF_DET_ERR bit active if VREF < 0.7 V | 9 | ||
| Internal clock frequency tolerance (614.4 kHz nominal) | -5 | 5 | % | Internal clock frequency 614.4 kHz | 9 | ||
| Logic input hysteresis | 0.2 | 0.6 | V | 1.65 V ≤ IOVDD ≤ 3.6 V | 9 | ||
| Logic input current | -1 | 1 | µA | VIN = IOVDD or GND | 9 | ||
| Floating state leakage current (logic outputs) | -1 | 1 | µA | 10 | |||
| IAVDD external reference, Gain = 1, all buffers off, Low Power Mode | IAVDD | 125 | 140 | µA | Low Power Mode; gain 1 (printed 'Gain = 12'); all buffers off | 10 | |
| IAVDD external reference, Gain = 2 to 8, Low Power Mode | IAVDD | 205 | 250 | µA | Low Power Mode; Gain = 2 to 8 | 10 | |
| IAVDD external reference, Gain = 16 to 128, Low Power Mode | IAVDD | 235 | 300 | µA | Low Power Mode; Gain = 16 to 128 | 10 | |
| IAVDD external reference, Gain = 1, all buffers off, Mid Power Mode | IAVDD | 150 | 170 | µA | Mid Power Mode; gain 1 (printed 'Gain = 12'); all buffers off | 10 | |
| IAVDD external reference, Gain = 2 to 8, Mid Power Mode | IAVDD | 275 | 345 | µA | Mid Power Mode; Gain = 2 to 8 | 10 | |
| IAVDD external reference, Gain = 16 to 128, Mid Power Mode | IAVDD | 330 | 430 | µA | Mid Power Mode; Gain = 16 to 128 | 10 | |
| IAVDD external reference, Gain = 1, all buffers off, Full Power Mode | IAVDD | 315 | 350 | µA | Full Power Mode; gain 1 (printed 'Gain = 12'); all buffers off | 10 | |
| IAVDD external reference, Gain = 2 to 8, Full Power Mode | IAVDD | 660 | 830 | µA | Full Power Mode; Gain = 2 to 8 | 10 | |
| IAVDD external reference, Gain = 16 to 128, Full Power Mode | IAVDD | 875 | 1200 | µA | Full Power Mode; Gain = 16 to 128 | 10 | |
| IAVDD increase due to internal reference | IAVDD | 50 | 70 | µA | Independent of power mode | 10 | |
| IIOVDD, Low Power Mode | IIOVDD | 20 | 35 | µA | Low Power Mode | 10 | |
| IIOVDD, Mid Power Mode | IIOVDD | 25 | 40 | µA | Mid Power Mode | 10 | |
| IIOVDD, Full Power Mode | IIOVDD | 55 | 80 | µA | Full Power Mode | 10 | |
| Standby current, LDOs on only | IAVDD | 7 | 15 | µA | LDOs on only | 11 | |
| Power-down current | IAVDD | 1 | 3 | µA | Independent of power mode | 11 | |
| SCLK high pulse width | t3 | 100 | ns | SCLK high pulse width | 11 | ||
| SCLK low pulse width | t4 | 100 | ns | SCLK low pulse width | 11 | ||
| CS falling edge to DOUT/RDY active time | t1 | 0 | 80 | ns | CS falling edge to DOUT/RDY active time | 11 | |
| CS falling edge to SCLK active edge setup time | t8 | 0 | ns | CS falling edge to SCLK active edge setup time | 12 | ||
| Data valid to SCLK edge setup time | t9 | 30 | ns | Data valid to SCLK edge setup time | 12 | ||
| Data valid to SCLK edge hold time | t10 | 25 | ns | Data valid to SCLK edge hold time | 12 | ||
| CS rising edge to SCLK edge hold time | t11 | 0 | ns | CS rising edge to SCLK edge hold time | 12 | ||
| Thermal resistance junction-to-ambient, 24-lead TSSOP | θJA | 128 | °C/W | Device soldered in circuit board (surface-mount) | 14 | ||
| Thermal resistance junction-to-case, 24-lead TSSOP | θJC | 42 | °C/W | 14 |
CAD (KiCad official)
- Symbol:
AD7124-4BRUZ-RL7 - Footprint:
Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm - 3D model: TSSOP-24 (KiCad packages3D, STEP)
- 3D model files:
ad7124-4bruz-rl7-etched.step/ad7124-4bruz-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7124-4bruz-rl7.step/ad7124-4bruz-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (93 pp, sha256
9f9df9294d9f4ad3, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).